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Searched refs:WREG8 (Results 1 – 16 of 16) sorted by relevance

/openbmc/linux/drivers/gpu/drm/mgag200/
H A Dmgag200_bmc.c17 WREG8(DAC_INDEX, MGA1064_GEN_IO_CTL); in mgag200_bmc_disable_vidrst()
23 WREG8(DAC_INDEX, MGA1064_GEN_IO_DATA); in mgag200_bmc_disable_vidrst()
33 WREG8(DAC_INDEX, MGA1064_SPAREREG); in mgag200_bmc_disable_vidrst()
44 WREG8(DAC_INDEX, MGA1064_SPAREREG); in mgag200_bmc_disable_vidrst()
58 WREG8(DAC_INDEX, MGA1064_SPAREREG); in mgag200_bmc_disable_vidrst()
71 WREG8(MGAREG_CRTCEXT_INDEX, 1); in mgag200_bmc_enable_vidrst()
73 WREG8(MGAREG_CRTCEXT_DATA, tmp | 0x88); in mgag200_bmc_enable_vidrst()
76 WREG8(DAC_INDEX, MGA1064_REMHEADCTL2); in mgag200_bmc_enable_vidrst()
79 WREG8(DAC_DATA, tmp); in mgag200_bmc_enable_vidrst()
85 WREG8(DAC_INDEX, MGA1064_REMHEADCTL2); in mgag200_bmc_enable_vidrst()
[all …]
H A Dmgag200_g200wb.c117 WREG8(MGAREG_CRTC_INDEX, 0x1e); in mgag200_g200wb_pixpllc_atomic_update()
120 WREG8(MGAREG_CRTC_DATA, tmp+1); in mgag200_g200wb_pixpllc_atomic_update()
124 WREG8(DAC_INDEX, MGA1064_PIX_CLK_CTL); in mgag200_g200wb_pixpllc_atomic_update()
127 WREG8(DAC_DATA, tmp); in mgag200_g200wb_pixpllc_atomic_update()
129 WREG8(DAC_INDEX, MGA1064_REMHEADCTL); in mgag200_g200wb_pixpllc_atomic_update()
132 WREG8(DAC_DATA, tmp); in mgag200_g200wb_pixpllc_atomic_update()
137 WREG8(MGAREG_MEM_MISC_WRITE, tmp); in mgag200_g200wb_pixpllc_atomic_update()
139 WREG8(DAC_INDEX, MGA1064_PIX_CLK_CTL); in mgag200_g200wb_pixpllc_atomic_update()
142 WREG8(DAC_DATA, tmp); in mgag200_g200wb_pixpllc_atomic_update()
147 WREG8(DAC_INDEX, MGA1064_VREF_CTL); in mgag200_g200wb_pixpllc_atomic_update()
[all …]
H A Dmgag200_g200ev.c121 WREG8(DAC_INDEX, MGA1064_PIX_CLK_CTL); in mgag200_g200ev_pixpllc_atomic_update()
124 WREG8(DAC_DATA, tmp); in mgag200_g200ev_pixpllc_atomic_update()
128 WREG8(MGAREG_MEM_MISC_WRITE, tmp); in mgag200_g200ev_pixpllc_atomic_update()
130 WREG8(DAC_INDEX, MGA1064_PIX_PLL_STAT); in mgag200_g200ev_pixpllc_atomic_update()
132 WREG8(DAC_DATA, tmp & ~0x40); in mgag200_g200ev_pixpllc_atomic_update()
134 WREG8(DAC_INDEX, MGA1064_PIX_CLK_CTL); in mgag200_g200ev_pixpllc_atomic_update()
137 WREG8(DAC_DATA, tmp); in mgag200_g200ev_pixpllc_atomic_update()
145 WREG8(DAC_INDEX, MGA1064_PIX_CLK_CTL); in mgag200_g200ev_pixpllc_atomic_update()
148 WREG8(DAC_DATA, tmp); in mgag200_g200ev_pixpllc_atomic_update()
152 WREG8(DAC_INDEX, MGA1064_PIX_CLK_CTL); in mgag200_g200ev_pixpllc_atomic_update()
[all …]
H A Dmgag200_drv.h38 #define WREG8(reg, v) iowrite8(v, ((void __iomem *)mdev->rmmio) + (reg)) macro
48 WREG8(MGA_MISC_OUT, v)
66 WREG8(ATTR_INDEX, reg); \
67 WREG8(ATTR_DATA, v); \
72 WREG8(MGAREG_SEQ_INDEX, reg); \
78 WREG8(MGAREG_SEQ_INDEX, reg); \
79 WREG8(MGAREG_SEQ_DATA, v); \
84 WREG8(MGAREG_CRTC_INDEX, reg); \
90 WREG8(MGAREG_CRTC_INDEX, reg); \
91 WREG8(MGAREG_CRTC_DATA, v); \
[all …]
H A Dmgag200_mode.c36 WREG8(DAC_INDEX + MGA1064_INDEX, 0); in mgag200_crtc_set_gamma_linear()
42 WREG8(DAC_INDEX + MGA1064_COL_PAL, i * 8 + i / 4); in mgag200_crtc_set_gamma_linear()
43 WREG8(DAC_INDEX + MGA1064_COL_PAL, i * 4 + i / 16); in mgag200_crtc_set_gamma_linear()
44 WREG8(DAC_INDEX + MGA1064_COL_PAL, i * 8 + i / 4); in mgag200_crtc_set_gamma_linear()
48 WREG8(DAC_INDEX + MGA1064_COL_PAL, 0); in mgag200_crtc_set_gamma_linear()
49 WREG8(DAC_INDEX + MGA1064_COL_PAL, i * 4 + i / 16); in mgag200_crtc_set_gamma_linear()
50 WREG8(DAC_INDEX + MGA1064_COL_PAL, 0); in mgag200_crtc_set_gamma_linear()
56 WREG8(DAC_INDEX + MGA1064_COL_PAL, i); in mgag200_crtc_set_gamma_linear()
57 WREG8(DAC_INDEX + MGA1064_COL_PAL, i); in mgag200_crtc_set_gamma_linear()
58 WREG8(DAC_INDEX + MGA1064_COL_PAL, i); in mgag200_crtc_set_gamma_linear()
[all …]
H A Dmgag200_g200eh.c117 WREG8(DAC_INDEX, MGA1064_PIX_CLK_CTL); in mgag200_g200eh_pixpllc_atomic_update()
120 WREG8(DAC_DATA, tmp); in mgag200_g200eh_pixpllc_atomic_update()
124 WREG8(MGAREG_MEM_MISC_WRITE, tmp); in mgag200_g200eh_pixpllc_atomic_update()
126 WREG8(DAC_INDEX, MGA1064_PIX_CLK_CTL); in mgag200_g200eh_pixpllc_atomic_update()
129 WREG8(DAC_DATA, tmp); in mgag200_g200eh_pixpllc_atomic_update()
139 WREG8(DAC_INDEX, MGA1064_PIX_CLK_CTL); in mgag200_g200eh_pixpllc_atomic_update()
143 WREG8(DAC_DATA, tmp); in mgag200_g200eh_pixpllc_atomic_update()
145 WREG8(DAC_INDEX, MGA1064_PIX_CLK_CTL); in mgag200_g200eh_pixpllc_atomic_update()
149 WREG8(DAC_DATA, tmp); in mgag200_g200eh_pixpllc_atomic_update()
H A Dmgag200_g200er.c142 WREG8(DAC_INDEX, MGA1064_PIX_CLK_CTL); in mgag200_g200er_pixpllc_atomic_update()
145 WREG8(DAC_DATA, tmp); in mgag200_g200er_pixpllc_atomic_update()
147 WREG8(DAC_INDEX, MGA1064_REMHEADCTL); in mgag200_g200er_pixpllc_atomic_update()
150 WREG8(DAC_DATA, tmp); in mgag200_g200er_pixpllc_atomic_update()
154 WREG8(MGAREG_MEM_MISC_WRITE, tmp); in mgag200_g200er_pixpllc_atomic_update()
156 WREG8(DAC_INDEX, MGA1064_PIX_CLK_CTL); in mgag200_g200er_pixpllc_atomic_update()
160 WREG8(DAC_DATA, tmp); in mgag200_g200er_pixpllc_atomic_update()
H A Dmgag200_i2c.c40 WREG8(DAC_INDEX, MGA1064_GEN_IO_DATA); in mga_i2c_read_gpio()
48 WREG8(DAC_INDEX, MGA1064_GEN_IO_CTL); in mga_i2c_set_gpio()
H A Dmgag200_drv.c186 WREG8(MGA_MISC_OUT, misc); in mgag200_device_init()
/openbmc/linux/drivers/gpu/drm/amd/amdgpu/
H A Dmxgpu_ai.c39 WREG8(AI_MAIBOX_CONTROL_RCV_OFFSET_BYTE, 2); in xgpu_ai_mailbox_send_ack()
44 WREG8(AI_MAIBOX_CONTROL_TRN_OFFSET_BYTE, val ? 1 : 0); in xgpu_ai_mailbox_set_valid()
H A Dmxgpu_nv.c38 WREG8(NV_MAIBOX_CONTROL_RCV_OFFSET_BYTE, 2); in xgpu_nv_mailbox_send_ack()
43 WREG8(NV_MAIBOX_CONTROL_TRN_OFFSET_BYTE, val ? 1 : 0); in xgpu_nv_mailbox_set_valid()
H A Damdgpu.h1170 #define WREG8(reg, v) amdgpu_mm_wreg8(adev, (reg), (v)) macro
/openbmc/linux/drivers/gpu/drm/radeon/
H A Dradeon_legacy_tv.c288 WREG8(RADEON_CLOCK_CNTL_INDEX, RADEON_PLL_TEST_CNTL); in radeon_wait_pll_lock()
290 WREG8(RADEON_CLOCK_CNTL_DATA + 3, 0); in radeon_wait_pll_lock()
H A Dr100.c2913 WREG8(RADEON_CLOCK_CNTL_INDEX, reg & 0x3f); in r100_pll_rreg()
2926 WREG8(RADEON_CLOCK_CNTL_INDEX, ((reg & 0x3f) | RADEON_PLL_WR_EN)); in r100_pll_wreg()
3807 WREG8(R_0003C2_GENMO_WT, C_0003C2_VGA_RAM_EN & save->GENMO_WT); in r100_mc_stop()
3838 WREG8(R_0003C2_GENMO_WT, save->GENMO_WT); in r100_mc_resume()
3851 WREG8(R_0003C2_GENMO_WT, C_0003C2_VGA_RAM_EN & tmp); in r100_vga_render_disable()
H A Dradeon_display.c72 WREG8(AVIVO_DC_LUT_RW_INDEX, 0); in avivo_crtc_load_lut()
209 WREG8(RADEON_PALETTE_INDEX, 0); in legacy_crtc_load_lut()
H A Dradeon.h2505 #define WREG8(reg, v) writeb(v, (rdev->rmmio) + (reg)) macro