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Searched refs:WREG32_SOC15_DPG_MODE (Results 1 – 6 of 6) sorted by relevance

/openbmc/linux/drivers/gpu/drm/amd/amdgpu/
H A Dvcn_v4_0_3.c473 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET( in vcn_v4_0_3_mc_resume_dpg_mode()
477 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET( in vcn_v4_0_3_mc_resume_dpg_mode()
481 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET( in vcn_v4_0_3_mc_resume_dpg_mode()
485 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET( in vcn_v4_0_3_mc_resume_dpg_mode()
487 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET( in vcn_v4_0_3_mc_resume_dpg_mode()
491 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET( in vcn_v4_0_3_mc_resume_dpg_mode()
494 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET( in vcn_v4_0_3_mc_resume_dpg_mode()
497 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET( in vcn_v4_0_3_mc_resume_dpg_mode()
738 WREG32_SOC15_DPG_MODE(inst_idx, 0xDEADBEEF, in vcn_v4_0_3_start_dpg_mode()
1759 WREG32_SOC15_DPG_MODE(inst_idx, in vcn_v4_0_3_enable_ras()
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H A Dvcn_v2_5.c532 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET( in vcn_v2_5_mc_resume_dpg_mode()
536 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET( in vcn_v2_5_mc_resume_dpg_mode()
539 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET( in vcn_v2_5_mc_resume_dpg_mode()
542 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET( in vcn_v2_5_mc_resume_dpg_mode()
544 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET( in vcn_v2_5_mc_resume_dpg_mode()
548 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET( in vcn_v2_5_mc_resume_dpg_mode()
551 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET( in vcn_v2_5_mc_resume_dpg_mode()
554 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET( in vcn_v2_5_mc_resume_dpg_mode()
804 WREG32_SOC15_DPG_MODE(inst_idx, in vcn_v2_6_enable_ras()
809 WREG32_SOC15_DPG_MODE(inst_idx, in vcn_v2_6_enable_ras()
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H A Dvcn_v2_0.c450 WREG32_SOC15_DPG_MODE(0, SOC15_DPG_MODE_OFFSET( in vcn_v2_0_mc_resume_dpg_mode()
454 WREG32_SOC15_DPG_MODE(0, SOC15_DPG_MODE_OFFSET( in vcn_v2_0_mc_resume_dpg_mode()
457 WREG32_SOC15_DPG_MODE(0, SOC15_DPG_MODE_OFFSET( in vcn_v2_0_mc_resume_dpg_mode()
460 WREG32_SOC15_DPG_MODE(0, SOC15_DPG_MODE_OFFSET( in vcn_v2_0_mc_resume_dpg_mode()
462 WREG32_SOC15_DPG_MODE(0, SOC15_DPG_MODE_OFFSET( in vcn_v2_0_mc_resume_dpg_mode()
466 WREG32_SOC15_DPG_MODE(0, SOC15_DPG_MODE_OFFSET( in vcn_v2_0_mc_resume_dpg_mode()
469 WREG32_SOC15_DPG_MODE(0, SOC15_DPG_MODE_OFFSET( in vcn_v2_0_mc_resume_dpg_mode()
472 WREG32_SOC15_DPG_MODE(0, SOC15_DPG_MODE_OFFSET( in vcn_v2_0_mc_resume_dpg_mode()
474 WREG32_SOC15_DPG_MODE(0, SOC15_DPG_MODE_OFFSET( in vcn_v2_0_mc_resume_dpg_mode()
479 WREG32_SOC15_DPG_MODE(0, SOC15_DPG_MODE_OFFSET( in vcn_v2_0_mc_resume_dpg_mode()
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H A Dvcn_v4_0.c501 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET( in vcn_v4_0_mc_resume_dpg_mode()
505 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET( in vcn_v4_0_mc_resume_dpg_mode()
508 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET( in vcn_v4_0_mc_resume_dpg_mode()
511 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET( in vcn_v4_0_mc_resume_dpg_mode()
513 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET( in vcn_v4_0_mc_resume_dpg_mode()
517 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET( in vcn_v4_0_mc_resume_dpg_mode()
520 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET( in vcn_v4_0_mc_resume_dpg_mode()
523 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET( in vcn_v4_0_mc_resume_dpg_mode()
525 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET( in vcn_v4_0_mc_resume_dpg_mode()
895 WREG32_SOC15_DPG_MODE(inst_idx, in vcn_v4_0_enable_ras()
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H A Dvcn_v3_0.c561 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET( in vcn_v3_0_mc_resume_dpg_mode()
565 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET( in vcn_v3_0_mc_resume_dpg_mode()
568 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET( in vcn_v3_0_mc_resume_dpg_mode()
571 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET( in vcn_v3_0_mc_resume_dpg_mode()
573 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET( in vcn_v3_0_mc_resume_dpg_mode()
577 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET( in vcn_v3_0_mc_resume_dpg_mode()
580 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET( in vcn_v3_0_mc_resume_dpg_mode()
583 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET( in vcn_v3_0_mc_resume_dpg_mode()
585 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET( in vcn_v3_0_mc_resume_dpg_mode()
590 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET( in vcn_v3_0_mc_resume_dpg_mode()
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H A Damdgpu_vcn.h144 #define WREG32_SOC15_DPG_MODE(inst_idx, offset, value, mask_en, indirect) \ macro