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Searched refs:WREG32_RLC (Results 1 – 7 of 7) sorted by relevance

/openbmc/linux/drivers/gpu/drm/amd/amdgpu/
H A Damdgpu_amdkfd_gc_9_4_3.c303 WREG32_RLC(reg, mqd_hqd[reg - hqd_base]); in kgd_gfx_v9_4_3_hqd_load()
309 WREG32_RLC(SOC15_REG_OFFSET(GC, GET_INST(GC, inst), regCP_HQD_PQ_DOORBELL_CONTROL), in kgd_gfx_v9_4_3_hqd_load()
339 WREG32_RLC(SOC15_REG_OFFSET(GC, GET_INST(GC, inst), regCP_HQD_PQ_WPTR_LO), in kgd_gfx_v9_4_3_hqd_load()
341 WREG32_RLC(SOC15_REG_OFFSET(GC, GET_INST(GC, inst), regCP_HQD_PQ_WPTR_HI), in kgd_gfx_v9_4_3_hqd_load()
343 WREG32_RLC(SOC15_REG_OFFSET(GC, GET_INST(GC, inst), regCP_HQD_PQ_WPTR_POLL_ADDR), in kgd_gfx_v9_4_3_hqd_load()
345 WREG32_RLC(SOC15_REG_OFFSET(GC, GET_INST(GC, inst), in kgd_gfx_v9_4_3_hqd_load()
354 WREG32_RLC(SOC15_REG_OFFSET(GC, GET_INST(GC, inst), regCP_HQD_EOP_RPTR), in kgd_gfx_v9_4_3_hqd_load()
359 WREG32_RLC(SOC15_REG_OFFSET(GC, GET_INST(GC, inst), regCP_HQD_ACTIVE), data); in kgd_gfx_v9_4_3_hqd_load()
497 WREG32_RLC((SOC15_REG_OFFSET(GC, GET_INST(GC, inst), in kgd_gfx_v9_4_3_set_address_watch()
502 WREG32_RLC((SOC15_REG_OFFSET(GC, GET_INST(GC, inst), in kgd_gfx_v9_4_3_set_address_watch()
H A Damdgpu_amdkfd_gfx_v9.c95 WREG32_RLC(SOC15_REG_OFFSET(GC, GET_INST(GC, inst), mmSH_MEM_BASES), sh_mem_bases); in kgd_gfx_v9_program_sh_mem_settings()
242 WREG32_RLC(reg, mqd_hqd[reg - hqd_base]); in kgd_gfx_v9_hqd_load()
278 WREG32_RLC(SOC15_REG_OFFSET(GC, GET_INST(GC, inst), mmCP_HQD_PQ_WPTR_LO), in kgd_gfx_v9_hqd_load()
280 WREG32_RLC(SOC15_REG_OFFSET(GC, GET_INST(GC, inst), mmCP_HQD_PQ_WPTR_HI), in kgd_gfx_v9_hqd_load()
291 WREG32_RLC(SOC15_REG_OFFSET(GC, GET_INST(GC, inst), mmCP_HQD_EOP_RPTR), in kgd_gfx_v9_hqd_load()
296 WREG32_RLC(SOC15_REG_OFFSET(GC, GET_INST(GC, inst), mmCP_HQD_ACTIVE), data); in kgd_gfx_v9_hqd_load()
856 WREG32_RLC((SOC15_REG_OFFSET(GC, 0, mmTCP_WATCH0_CNTL) + in kgd_gfx_v9_set_address_watch()
860 WREG32_RLC((SOC15_REG_OFFSET(GC, 0, mmTCP_WATCH0_ADDR_H) + in kgd_gfx_v9_set_address_watch()
864 WREG32_RLC((SOC15_REG_OFFSET(GC, 0, mmTCP_WATCH0_ADDR_L) + in kgd_gfx_v9_set_address_watch()
874 WREG32_RLC((SOC15_REG_OFFSET(GC, 0, mmTCP_WATCH0_CNTL) + in kgd_gfx_v9_set_address_watch()
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H A Damdgpu_amdkfd_aldebaran.c155 WREG32_RLC((SOC15_REG_OFFSET(GC, 0, regTCP_WATCH0_ADDR_H) + in kgd_gfx_aldebaran_set_address_watch()
159 WREG32_RLC((SOC15_REG_OFFSET(GC, 0, regTCP_WATCH0_ADDR_L) + in kgd_gfx_aldebaran_set_address_watch()
H A Damdgpu_amdkfd_gfx_v11.c772 WREG32_RLC((SOC15_REG_OFFSET(GC, 0, regTCP_WATCH0_ADDR_H) + in kgd_gfx_v11_set_address_watch()
776 WREG32_RLC((SOC15_REG_OFFSET(GC, 0, regTCP_WATCH0_ADDR_L) + in kgd_gfx_v11_set_address_watch()
H A Dsoc15_common.h110 #define WREG32_RLC(reg, value) \ macro
H A Dsoc15.c473 WREG32_RLC(reg, tmp); in soc15_program_register_sequence()
H A Dgfx_v9_0.c2491 WREG32_RLC(SOC15_REG_OFFSET(GC, 0, mmRLC_CSIB_ADDR_HI), in gfx_v9_0_init_csb()
2493 WREG32_RLC(SOC15_REG_OFFSET(GC, 0, mmRLC_CSIB_ADDR_LO), in gfx_v9_0_init_csb()
2495 WREG32_RLC(SOC15_REG_OFFSET(GC, 0, mmRLC_CSIB_LENGTH), in gfx_v9_0_init_csb()