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/openbmc/openbmc/meta-openembedded/meta-oe/dynamic-layers/selinux/recipes-devtool/android-tools/android-tools/debian/system/core/
H A DVector-cast.patch6 --- a/system/core/libutils/include/utils/Vector.h
7 +++ b/system/core/libutils/include/utils/Vector.h
11 const Vector<TYPE>& Vector<TYPE>::operator = (const Vector<TYPE>& rhs) const {
/openbmc/openbmc/meta-openembedded/meta-oe/dynamic-layers/selinux/recipes-devtool/android-tools/android-tools/debian/
H A DVector-cast.patch6 --- a/system/core/libutils/include/utils/Vector.h
7 +++ b/system/core/libutils/include/utils/Vector.h
11 const Vector<TYPE>& Vector<TYPE>::operator = (const Vector<TYPE>& rhs) const {
/openbmc/openbmc/poky/meta/conf/machine/include/arm/
H A Dfeature-arm-neon.inc10 TUNEVALID[vfpv3d16] = "Enable Vector Floating Point Version 3 with 16 registers (vfpv3-d16) unit."
13 TUNEVALID[vfpv3] = "Enable Vector Floating Point Version 3 with 32 registers (vfpv3) unit."
16 TUNEVALID[vfpv4] = "Enable Vector Floating Point Version 4 (vfpv4) unit."
20 TUNEVALID[vfpv4d16] = "Enable Vector Floating Point Version 4 with 16 registers (vfpv4-d16) unit."
23 TUNEVALID[vfpv5spd16] = "Enable Vector Floating Point Version 5, Single Precision. with 16 register…
H A Dfeature-arm-sve.inc1 # Scalable Vector Extension (SVE) for Armv8-A and R
H A Dfeature-arm-vfp.inc5 TUNEVALID[vfp] = "Enable Vector Floating Point (vfp) unit."
/openbmc/qemu/target/hexagon/imported/mmvec/
H A Dext.idef212 "Vector shift right and shuffle", \
218 …Vv32)", "Vd32."#DEST"=vavg(Vu32."#SRC",Vv32."#SRC")", "Vector Average "DESCR, …
219 …Vv32):rnd", "Vd32."#DEST"=vavg(Vu32."#SRC",Vv32."#SRC"):rnd", "Vector Average % Round"DE…
220 …,Vv32)", "Vd32."#DEST"=vnavg(Vu32."#SRC",Vv32."#SRC")", "Vector Negative Average "…
223 …32,Vv32)", "Vd32."#DEST"=vavg(Vu32."#SRC",Vv32."#SRC")", "Vector Average "DESCR, …
224 …32,Vv32):rnd", "Vd32."#DEST"=vavg(Vu32."#SRC",Vv32."#SRC"):rnd", "Vector Average % Round"DE…
276 MMVEC_LD(vL32b, "Aligned Vector Load", ATTRIBS(ATTR_VMEM,A_LOAD,A_CVI_VA),)
277 MMVEC_LDC(vL32b, "Aligned Vector Load Cur", ATTRIBS(ATTR_VMEM,A_LOAD,A_CVI_NEW,A_CVI_VA),)
278 MMVEC_LDT(vL32b, "Aligned Vector Load Tmp", ATTRIBS(ATTR_VMEM,A_LOAD,A_CVI_TMP),)
280 MMVEC_COND_EACH_EA(vL32b,"Conditional Aligned Vector Load",ATTRIBS(ATTR_VMEM,A_LOAD,A_CVI_VA),,"Vd3…
[all …]
/openbmc/qemu/target/hexagon/imported/
H A Dshift.idef199 ATTRIBS(), "Vector align bytes",
209 ATTRIBS(), "Vector splice bytes",
217 ATTRIBS(), "Vector splat halfwords from register",
227 ATTRIBS(), "Vector splat bytes from register",
236 ATTRIBS(), "Vector splat bytes from register",
517 /* Half Vector Immediate Shifts */
520 "Vector Arithmetic Shift Right by Immediate",
530 "Vector Logical Shift Right by Immediate",
539 "Vector Arithmetic Shift Left by Immediate",
547 /* Half Vector Register Shifts */
[all …]
H A Dmpy.idef207 Q6INSN(M2_vmpy2s_s0,"Rdd32=vmpyh(Rs32,Rt32):sat",ATTRIBS(),"Vector Multiply",vmac_sema(0))
208 Q6INSN(M2_vmpy2s_s1,"Rdd32=vmpyh(Rs32,Rt32):<<1:sat",ATTRIBS(),"Vector Multiply",vmac_sema(1))
216 Q6INSN(M2_vmac2s_s0,"Rxx32+=vmpyh(Rs32,Rt32):sat",ATTRIBS(),"Vector Multiply",vmac_sema(0))
217 Q6INSN(M2_vmac2s_s1,"Rxx32+=vmpyh(Rs32,Rt32):<<1:sat",ATTRIBS(),"Vector Multiply",vmac_sema(1))
224 Q6INSN(M2_vmpy2su_s0,"Rdd32=vmpyhsu(Rs32,Rt32):sat",ATTRIBS(),"Vector Multiply",vmac_sema(0))
225 Q6INSN(M2_vmpy2su_s1,"Rdd32=vmpyhsu(Rs32,Rt32):<<1:sat",ATTRIBS(),"Vector Multiply",vmac_sema(1))
233 Q6INSN(M2_vmac2su_s0,"Rxx32+=vmpyhsu(Rs32,Rt32):sat",ATTRIBS(),"Vector Multiply",vmac_sema(0))
234 Q6INSN(M2_vmac2su_s1,"Rxx32+=vmpyhsu(Rs32,Rt32):<<1:sat",ATTRIBS(),"Vector Multiply",vmac_sema(1))
243 Q6INSN(M2_vmpy2s_s0pack,"Rd32=vmpyh(Rs32,Rt32):rnd:sat",ATTRIBS(A_ARCHV2),"Vector Multiply",vmac_se…
244 Q6INSN(M2_vmpy2s_s1pack,"Rd32=vmpyh(Rs32,Rt32):<<1:rnd:sat",ATTRIBS(A_ARCHV2),"Vector Multiply",vma…
[all …]
H A Dalu.idef183 "Vector Complex conjugate of Rss",
487 /* Vector Add */
627 /* 1/2 Vector operations */
720 /* Vector Reduce Add */
771 /* Vector Sub */
841 /* Vector Abs */
881 /* Vector SAD */
950 /* Vector Average */
1184 /* V4: Cross Vector Min/Max */
1219 /* Vector Min/Max */
[all …]
/openbmc/qemu/target/ppc/
H A Dinsn32.decode663 ## Vector Exclusive-OR-based Instructions
667 ## Vector Load/Store Instructions
684 ## Vector Integer Instructions
715 ## Vector Integer Logical Instructions
726 ## Vector Integer Average Instructions
735 ## Vector Integer Absolute Difference Instructions
741 ## Vector Bit Manipulation Instruction
755 ## Vector Permute and Formatting Instruction
798 ## Vector Integer Shift Instruction
832 ## Vector Integer Arithmetic Instructions
[all …]
/openbmc/qemu/docs/system/arm/
H A Demulation.rst139 - FEAT_SVE (Scalable Vector Extension)
140 - FEAT_SVE_AES (Scalable Vector AES instructions)
142 - FEAT_SVE_BitPerm (Scalable Vector Bit Permutes instructions)
143 - FEAT_SVE_PMULL128 (Scalable Vector PMULL instructions)
144 - FEAT_SVE_SHA3 (Scalable Vector SHA3 instructions)
145 - FEAT_SVE_SM4 (Scalable Vector SM4 instructions)
146 - FEAT_SVE2 (Scalable Vector Extension version 2)
147 - FEAT_SVE2p1 (Scalable Vector Extension version 2.1)
/openbmc/qemu/target/riscv/insn_trans/
H A Dtrans_rvv.c.inc139 * Vector register should aligned with the passed-in LMUL (EMUL).
263 * Vector unit-stride, strided, unit-stride segment, strided segment
271 * 4. Vector register numbers accessed by the segment load or store
283 * Vector unit-stride, strided, unit-stride segment, strided segment
300 * Vector indexed, indexed segment store check function.
309 * 5. Vector register numbers accessed by the segment load or store
334 * Vector indexed, indexed segment load check function.
759 * Vector load/store instructions have the EEW encoded
1300 *** Vector Integer Arithmetic Instructions
1599 /* Vector Widening Integer Add/Subtract */
[all …]
/openbmc/qemu/target/riscv/
H A Dinsn32.decode365 # *** Vector loads and stores are encoded within LOADFP/STORE-FP ***
366 # Vector unit-stride load/store insns.
376 # Vector unit-stride mask load/store insns.
380 # Vector strided insns.
390 # Vector ordered-indexed and unordered-indexed load insns.
396 # Vector ordered-indexed and unordered-indexed store insns.
402 # Vector unit-stride fault-only-first load insns.
408 # Vector whole register insns
698 # Vector ordered and unordered reduction sum
703 # Vector widening ordered and unordered float reduction sum
[all …]
/openbmc/u-boot/arch/x86/cpu/
H A Du-boot-spl.lds60 * Reset Vector at the end of the Flash ROM
H A Du-boot.lds112 * Reset Vector at the end of the Flash ROM
/openbmc/phosphor-inventory-manager/
H A Dpimgen.py234 class Vector(MethodCall): class
241 super(Vector, self).__init__(**kw)
479 filters = Vector(
495 events = Vector(
505 actions = Vector(templates=[action_type], args=action_args)
/openbmc/u-boot/doc/imx/habv4/guides/
H A Dmx6_mx7_spl_secure_boot.txt36 The U-Boot also append an Image Vector Table (IVT) in the final U-Boot proper
42 ^ | Image Vector Table |
72 v | Image Vector Table |
H A Dmx6_mx7_secure_boot.txt33 ^ | Image Vector Table |
329 v | Image Vector Table |
351 2.2 Generating Image Vector Table
354 The HAB code requires an Image Vector Table (IVT) for determining the image
H A Dencrypted_boot.txt6 u-boot-dtb.imx with the encrypted data. The Initial Vector Table,
/openbmc/u-boot/arch/powerpc/dts/
H A De6500_power_isa.dtsi34 power-isa-v; // Vector (AltiVec)
/openbmc/qemu/docs/specs/
H A Dsev-guest-firmware.rst32 `OVMF Reset Vector file`_.
124 .. _OVMF Reset Vector file:
/openbmc/u-boot/doc/
H A DREADME.N121313 - Vector interrupts for internal/external.
/openbmc/qemu/target/arm/tcg/
H A Dmve.decode121 # Vector comparison; 4-bit Qm but 3-bit Qn
155 # Vector loads and stores
210 # Vector 2-op
369 # Vector miscellaneous
575 # Vector add across vector
/openbmc/qemu/target/s390x/
H A Dcpu_features_def.h.inc97 DEF_FEAT(VECTOR, "vx", STFL, 129, "Vector facility")
101 DEF_FEAT(VECTOR_PACKED_DECIMAL, "vxpd", STFL, 134, "Vector packed decimal facility")
102 DEF_FEAT(VECTOR_ENH, "vxeh", STFL, 135, "Vector enhancements facility")
109 DEF_FEAT(VECTOR_ENH2, "vxeh2", STFL, 148, "Vector Enhancements facility 2")
112 DEF_FEAT(VECTOR_PACKED_DECIMAL_ENH, "vxpdeh", STFL, 152, "Vector-Packed-Decimal-Enhancement Facilit…
118 DEF_FEAT(VECTOR_PACKED_DECIMAL_ENH2, "vxpdeh2", STFL, 192, "Vector-Packed-Decimal-Enhancement facil…
123 DEF_FEAT(VECTOR_ENH3, "vxeh3", STFL, 198, "Vector Enhancements facility 3")
124 DEF_FEAT(VECTOR_PACKED_DECIMAL_ENH3, "vxpdeh3", STFL, 199, "Vector-Packed-Decimal-Enhancement facil…
/openbmc/phosphor-power/phosphor-power-supply/docs/
H A DMultiChassis.md39 - Vector of powerSupply instances

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