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Searched refs:VC3_MPAR_CL (Results 1 – 1 of 1) sorted by relevance

/openbmc/u-boot/arch/mips/mach-mscc/include/mach/
H A Dddr.h25 #define VC3_MPAR_CL 6 macro
48 #define VC3_MPAR_CL 5 macro
71 #define VC3_MPAR_CL 5 macro
94 #define VC3_MPAR_CL 6 macro
117 #define VC3_MPAR_CL 6 macro
140 #define VC3_MPAR_CL 4 macro
197 #define VC3_MPAR_RL VC3_MPAR_CL
292 ICPU_MEMCTRL_TIMING0_WR_TO_PRECH_DLY(VC3_MPAR_CL + \
297 ICPU_MEMCTRL_TIMING0_RD_DATA_XFR_DLY(VC3_MPAR_CL - 3)
305 ICPU_MEMCTRL_TIMING1_WR_TO_RD_DLY(VC3_MPAR_CL + \
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