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Searched refs:V7M_CCR_ICACHE (Results 1 – 2 of 2) sorted by relevance

/openbmc/u-boot/arch/arm/cpu/armv7m/
H A Dcache.c312 setbits_le32(&V7M_SCB->ccr, BIT(V7M_CCR_ICACHE)); in icache_enable()
321 return (readl(&V7M_SCB->ccr) & BIT(V7M_CCR_ICACHE)) != 0; in icache_status()
330 clrbits_le32(&V7M_SCB->ccr, BIT(V7M_CCR_ICACHE)); in icache_disable()
/openbmc/u-boot/arch/arm/include/asm/
H A Darmv7m.h56 #define V7M_CCR_ICACHE 17 macro