| /openbmc/u-boot/drivers/serial/ |
| H A D | Kconfig | 12 meaning of either setting the baudrate for the early debug UART
32 In various cases, we need to specify which of the UART devices that
41 In very space-constrained devices even the full UART driver is too
42 large. In this case the debug UART can still be used in some cases.
43 This option enables the full UART in U-Boot, so if is it disabled,
44 the full UART driver will be omitted, thus saving space.
51 In very space-constrained devices even the full UART driver is too
52 large. In this case the debug UART can still be used in some cases.
53 This option enables the full UART in SPL, so if is it disabled,
54 the full UART driver will be omitted, thus saving space.
[all …]
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| H A D | serial_pxa.c | 177 #define pxa_uart(uart, UART) \ argument
180 return pxa_init_dev(UART##_INDEX); \
185 return pxa_setbrg_dev(UART##_INDEX); \
190 return pxa_putc_dev(UART##_INDEX, c); \
195 return pxa_puts_dev(UART##_INDEX, s); \
200 return pxa_getc_dev(UART##_INDEX); \
205 return pxa_tstc_dev(UART##_INDEX); \
221 #define pxa_uart_multi(uart, UART) \ argument
222 pxa_uart(uart, UART) \
|
| /openbmc/u-boot/board/congatec/conga-qeval20-qa3-e3845/ |
| H A D | README | 2 U-Boot console UART selection:
6 configurations (defconfig files). The only difference is the UART that
7 is used as the U-Boot console UART. The default defconfig file:
13 board (conga-QEVAL). This UART is the one provided with a SubD9
18 provides the U-Boot console on the BayTrail internal legacy UART,
21 RS232 level shifters. So a TTL-USB UART adapter does not work in
23 RS232 level signals of the PC UART via some adapter cable.
|
| /openbmc/u-boot/arch/arm/ |
| H A D | Kconfig.debug | 16 bool "Low-level debugging via 8250 UART"
19 their output to an 8250 UART. You can use this option
20 to provide the parameters for the 8250 UART rather than
41 hex "Physical base address of debug UART"
51 int "Register offset shift for the 8250 debug UART"
56 bool "Use 32-bit accesses for 8250 UART"
61 bool "Enable flow control for 8250 UART"
|
| /openbmc/phosphor-dbus-interfaces/gen/xyz/openbmc_project/Console/ |
| H A D | meson.build | 3 subdir('UART') subdir
34 '../../../../yaml/xyz/openbmc_project/Console/UART.interface.yaml',
36 output: ['UART.md'],
48 'xyz/openbmc_project/Console/UART',
|
| /openbmc/u-boot/board/solidrun/clearfog/ |
| H A D | README | 29 - UART: 01001 [1]
31 [1]: According to SolidRun's manual, 11110 should be used for UART booting on
36 Boot from UART:
42 Set the SW1 DIP switches to UART boot (see above).
48 Use the correct UART device node for /dev/ttyUSBX.
|
| /openbmc/phosphor-dbus-interfaces/gen/xyz/openbmc_project/Console/UART/ |
| H A D | meson.build | 3 sdbusplus_current_path = 'xyz/openbmc_project/Console/UART'
8 '../../../../../yaml/xyz/openbmc_project/Console/UART.interface.yaml',
28 'xyz/openbmc_project/Console/UART',
|
| /openbmc/qemu/docs/system/arm/ |
| H A D | mps2.rst | 70 Note that for the AN536 the first UART is accessible only by
71 CPU0, and the second UART is accessible only by CPU1. The
72 first UART accessible shared between both CPUs is the third
73 UART. Guest software might therefore be built to use either
74 the first UART or the third UART; if you don't see any output
75 from the UART you are looking at, try one of the others.
77 no "CPU1-only UART", the UART numbering remains the same,
78 with the third UART being the first of the shared ones.)
|
| /openbmc/u-boot/board/kobol/helios4/ |
| H A D | README | 29 - UART: 11110
31 Boot from UART:
37 Set the SW1 DIP switches to UART boot (see above).
43 Use the correct UART device node for /dev/ttyUSBX.
|
| /openbmc/u-boot/doc/device-tree-bindings/serial/ |
| H A D | altera_uart.txt | 1 Altera UART
7 - clock-frequency : frequency of the clock input to the UART
|
| H A D | 8250.txt | 1 * UART (Universal Asynchronous Receiver/Transmitter)
26 - clock-frequency : the input clock frequency for the UART
32 - current-speed : the current active speed of the UART.
37 accesses to the UART (e.g. TI davinci).
42 - fifo-size: the fifo size of the UART.
|
| H A D | xilinx_uartlite.txt | 5 - reg: Should contain UART controller registers location and length.
6 - interrupts: Should contain UART controller interrupts.
|
| H A D | bcm2835-aux-uart.txt | 1 * BCM283x mini UART
6 - clock: input clock frequency for the UART (used to calculate the baud
|
| H A D | pl01x.txt | 1 * ARM AMBA Primecell PL011 & PL010 serial UART
6 - clock: input clock frequency for the UART (used to calculate the baud
|
| H A D | qca,ar9330-uart.txt | 1 * Qualcomm Atheros AR9330 High-Speed UART
12 Each UART port must have an alias correctly numbered in "aliases"
|
| /openbmc/u-boot/arch/x86/cpu/baytrail/ |
| H A D | Kconfig | 31 bool "Enable the SoC integrated legacy UART"
33 There is a legacy UART integrated into the Bay Trail SoC.
35 reason, it is recommended that the UART port be used for
|
| /openbmc/obmc-console/ |
| H A D | CHANGELOG.md | 24 3. UART multiplexer support
58 4. Implement D-Bus interface `xyz.openbmc_project.Console.UART` for UART TTY
64 underlying TTY device is a UART and not a VUART nor PTY (where baud is not
80 functionally equivalent `xyz.openbmc_project.Console.UART`.
|
| /openbmc/u-boot/arch/arm/dts/ |
| H A D | kirkwood-openrd.dtsi | 61 * mode for the second UART.
66 * To use the second UART, you need to change also
78 * SelUARTorSD selects between the second UART
81 * Low: UART
|
| H A D | meson-gxl-s905x-khadas-vim.dts | 117 gpio-line-names = "UART TX",
118 "UART RX",
164 "Bluetooth UART TX", "Bluetooth UART RX",
165 "Bluetooth UART CTS", "Bluetooth UART RTS",
|
| /openbmc/u-boot/arch/mips/mach-bmips/ |
| H A D | Kconfig | 137 ethernet ports, 2 USB ports, 1 UART, GPIO buttons and LEDs, and
148 ethernet ports, 1 USB port, 1 UART, GPIO buttons and LEDs, and
159 ethernet ports, 1 USB port, 1 UART, GPIO buttons and LEDs, and
170 ethernet ports, 1 USB port, 1 UART, GPIO buttons and LEDs, and a
181 ethernet ports, 1 USB port, 1 UART, GPIO buttons and LEDs,
192 ethernet ports, 1 USB port, 1 UART, GPIO buttons and LEDs,
203 ethernet ports, 3 USB ports, 1 UART, GPIO buttons and LEDs, and
214 ethernet ports, 1 UART, GPIO buttons and LEDs, and a BCM43225
225 ethernet ports, 2 USB ports, 1 UART, GPIO buttons and LEDs, and a
236 ethernet ports, 1 UART, GPIO buttons and LEDs, and a BCM4312
[all …]
|
| /openbmc/openbmc/meta-raspberrypi/recipes-connectivity/pi-bluetooth/pi-bluetooth/ |
| H A D | 0001-bthelper-correct-path-for-hciconfig-under-Yocto.patch | 23 -if ! /bin/hciconfig $dev | grep -q "Bus: UART"; then
25 +if ! /usr/bin/hciconfig $dev | grep -q "Bus: UART"; then
26 echo Not a UART-attached BT Modem
|
| /openbmc/docs/ |
| H A D | console.md | 3 This document describes how to connect to the host UART console from an OpenBMC
7 UART. UART data from the host is output to all connections, and input from any
|
| /openbmc/u-boot/arch/arm/mach-bcm283x/ |
| H A D | Kconfig | 54 mini UART (rather than PL011) for the serial console. This is the
55 default on the RPi Zero W. To enable the UART console, the following
71 VideoCore firmware to select the PL011 UART for the console by:
93 mini UART (rather than PL011) for the serial console. This is the
94 default on the RPi 3. To enable the UART console, the following non-
109 mini UART (rather than PL011) for the serial console. This is the
110 default on the RPi 3. To enable the UART console, the following non-
|
| /openbmc/u-boot/board/freescale/ls1012ardb/ |
| H A D | README | 35 - UART
36 - The LS1012A processor consists of two UART controllers,
71 - UART
72 - The LS1012A processor consists of two UART controllers,
|
| /openbmc/u-boot/board/freescale/ls1012afrdm/ |
| H A D | README | 30 - UART
31 - UART (Console): UART1 (Without flow control) for console
40 - 24 MHz for SC16IS740IPW SPI to Dual UART bridge
|