175219d57SThomas Chou* UART (Universal Asynchronous Receiver/Transmitter)
275219d57SThomas Chou
375219d57SThomas ChouRequired properties:
475219d57SThomas Chou- compatible : one of:
575219d57SThomas Chou	- "ns8250"
675219d57SThomas Chou	- "ns16450"
775219d57SThomas Chou	- "ns16550a"
875219d57SThomas Chou	- "ns16550"
975219d57SThomas Chou	- "ns16750"
1075219d57SThomas Chou	- "ns16850"
1175219d57SThomas Chou	- For Tegra20, must contain "nvidia,tegra20-uart"
1275219d57SThomas Chou	- For other Tegra, must contain '"nvidia,<chip>-uart",
1375219d57SThomas Chou	  "nvidia,tegra20-uart"' where <chip> is tegra30, tegra114, tegra124,
1475219d57SThomas Chou	  tegra132, or tegra210.
1575219d57SThomas Chou	- "nxp,lpc3220-uart"
1675219d57SThomas Chou	- "ralink,rt2880-uart"
1775219d57SThomas Chou	- "ibm,qpace-nwp-serial"
1875219d57SThomas Chou	- "altr,16550-FIFO32"
1975219d57SThomas Chou	- "altr,16550-FIFO64"
2075219d57SThomas Chou	- "altr,16550-FIFO128"
2175219d57SThomas Chou	- "fsl,16550-FIFO64"
2275219d57SThomas Chou	- "fsl,ns16550"
2375219d57SThomas Chou	- "serial" if the port type is unknown.
2475219d57SThomas Chou- reg : offset and length of the register set for the device.
2575219d57SThomas Chou- interrupts : should contain uart interrupt.
2675219d57SThomas Chou- clock-frequency : the input clock frequency for the UART
2775219d57SThomas Chou	 or
2875219d57SThomas Chou  clocks phandle to refer to the clk used as per Documentation/devicetree
2975219d57SThomas Chou  /bindings/clock/clock-bindings.txt
3075219d57SThomas Chou
3175219d57SThomas ChouOptional properties:
3275219d57SThomas Chou- current-speed : the current active speed of the UART.
3375219d57SThomas Chou- reg-offset : offset to apply to the mapbase from the start of the registers.
3475219d57SThomas Chou- reg-shift : quantity to shift the register offsets by.
3575219d57SThomas Chou- reg-io-width : the size (in bytes) of the IO accesses that should be
3675219d57SThomas Chou  performed on the device.  There are some systems that require 32-bit
3775219d57SThomas Chou  accesses to the UART (e.g. TI davinci).
3875219d57SThomas Chou- used-by-rtas : set to indicate that the port is in use by the OpenFirmware
3975219d57SThomas Chou  RTAS and should not be registered.
4075219d57SThomas Chou- no-loopback-test: set to indicate that the port does not implements loopback
4175219d57SThomas Chou  test mode
4275219d57SThomas Chou- fifo-size: the fifo size of the UART.
4375219d57SThomas Chou- auto-flow-control: one way to enable automatic flow control support. The
4475219d57SThomas Chou  driver is allowed to detect support for the capability even without this
4575219d57SThomas Chou  property.
4675219d57SThomas Chou
4775219d57SThomas ChouNote:
4875219d57SThomas Chou* fsl,ns16550:
4975219d57SThomas Chou  ------------
5075219d57SThomas Chou  Freescale DUART is very similar to the PC16552D (and to a
5175219d57SThomas Chou  pair of NS16550A), albeit with some nonstandard behavior such as
5275219d57SThomas Chou  erratum A-004737 (relating to incorrect BRK handling).
5375219d57SThomas Chou
5475219d57SThomas Chou  Represents a single port that is compatible with the DUART found
5575219d57SThomas Chou  on many Freescale chips (examples include mpc8349, mpc8548,
56*3c1d218aSYork Sun  mpc8641d, p4080 and ls2080a).
5775219d57SThomas Chou
5875219d57SThomas ChouExample:
5975219d57SThomas Chou
6075219d57SThomas Chou	uart@80230000 {
6175219d57SThomas Chou		compatible = "ns8250";
6275219d57SThomas Chou		reg = <0x80230000 0x100>;
6375219d57SThomas Chou		clock-frequency = <3686400>;
6475219d57SThomas Chou		interrupts = <10>;
6575219d57SThomas Chou		reg-shift = <2>;
6675219d57SThomas Chou	};
67