Searched refs:TO_REG (Results 1 – 12 of 12) sorted by relevance
24 #define TO_REG(offset) ((offset) >> 2) macro26 #define PROT_KEY TO_REG(0x00)27 #define SYS_RST_CTRL TO_REG(0x04)28 #define CLK_SEL TO_REG(0x08)29 #define CLK_STOP_CTRL TO_REG(0x0C)135 #define AST2600_CLK TO_REG(0x40)250 int reg = TO_REG(offset); in aspeed_scu_read()281 int reg = TO_REG(offset); in aspeed_ast2400_scu_write()320 int reg = TO_REG(offset); in aspeed_ast2500_scu_write()615 int reg = TO_REG(offset); in aspeed_ast2600_scu_read()[all …]
20 #define TO_REG(offset) ((offset) >> 2) macro22 #define HICR0 TO_REG(0x00)26 #define HICR1 TO_REG(0x04)27 #define HICR2 TO_REG(0x08)31 #define HICR3 TO_REG(0x0C)32 #define HICR4 TO_REG(0x10)34 #define IDR1 TO_REG(0x24)35 #define IDR2 TO_REG(0x28)36 #define IDR3 TO_REG(0x2C)314 int reg = TO_REG(offset); in aspeed_lpc_read()[all …]
26 #define TO_REG(o) (o >> 2) macro179 if ((ibt->regs[TO_REG(BT_CTRL)] & BT_CTRL_H2B_ATN) && in aspeed_ibt_update_irq()181 ibt->regs[TO_REG(BT_CR2)] |= BT_CR2_IRQ_H2B; in aspeed_ibt_update_irq()192 if ((ibt->regs[TO_REG(BT_CTRL)] & BT_CTRL_H_BUSY) && in aspeed_ibt_update_irq()194 ibt->regs[TO_REG(BT_CR2)] |= BT_CR2_IRQ_HBUSY; in aspeed_ibt_update_irq()279 ibt->regs[TO_REG(BT_CTRL)] |= BT_CTRL_H2B_ATN; in vm_handle_char()406 ibt->regs[TO_REG(BT_CTRL)] &= ~BT_CTRL_H2B_ATN; in aspeed_ibt_write()412 ibt->regs[TO_REG(BT_CTRL)] ^= BT_CTRL_B_BUSY; in aspeed_ibt_write()461 ibt->regs[TO_REG(offset)] = (uint32_t) data; in aspeed_ibt_write()464 ibt->regs[TO_REG(offset)] ^= (uint32_t) data; in aspeed_ibt_write()[all …]
48 #define TO_REG(addr) ((addr) / sizeof(uint32_t)) macro56 val = xdma->regs[TO_REG(addr)]; in aspeed_xdma_read()75 xdma->regs[TO_REG(addr)] = val32 & XDMA_BMC_CMDQ_W_MASK; in aspeed_xdma_write()77 idx = TO_REG(addr); in aspeed_xdma_write()79 xdma->regs[TO_REG(axc->cmdq_rdp)] = xdma->regs[idx]; in aspeed_xdma_write()86 xdma->regs[TO_REG(axc->intr_status)] |= axc->intr_complete; in aspeed_xdma_write()88 if (xdma->regs[TO_REG(axc->intr_ctrl)] & axc->intr_complete) { in aspeed_xdma_write()99 xdma->regs[TO_REG(addr)] = val32 & axc->intr_ctrl_mask; in aspeed_xdma_write()103 idx = TO_REG(addr); in aspeed_xdma_write()109 xdma->regs[TO_REG(addr)] = val32; in aspeed_xdma_write()[all …]
17 #define TO_REG(x) (x >> 2) macro19 #define APB2OPB_VERSION TO_REG(0x00)20 #define APB2OPB_TRIGGER TO_REG(0x04)22 #define APB2OPB_CONTROL TO_REG(0x08)25 #define APB2OPB_OPB2FSI TO_REG(0x0c)28 #define APB2OPB_OPB0_SEL TO_REG(0x10)29 #define APB2OPB_OPB1_SEL TO_REG(0x28)61 #define APB2OPB_OPB0_READ_DATA TO_REG(0x84)62 #define APB2OPB_OPB1_READ_DATA TO_REG(0x90)99 unsigned int reg = TO_REG(addr); in fsi_aspeed_apb2opb_read()[all …]
17 #define TO_REG(x) ((x) >> 2) macro19 #define FSI_MENP0 TO_REG(0x010)20 #define FSI_MENP32 TO_REG(0x014)21 #define FSI_MSENP0 TO_REG(0x018)22 #define FSI_MLEVP0 TO_REG(0x018)23 #define FSI_MSENP32 TO_REG(0x01c)24 #define FSI_MLEVP32 TO_REG(0x01c)25 #define FSI_MCENP0 TO_REG(0x020)50 return s->regs[TO_REG(addr)]; in fsi_master_read()67 switch (TO_REG(addr)) { in fsi_master_write()[all …]
17 #define TO_REG(x) ((x) >> 2) macro32 return s->regs[TO_REG(addr)]; in fsi_slave_read()49 s->regs[TO_REG(addr)] = data; in fsi_slave_write()
23 #define TO_REG(x) ((x) >> 2) macro25 #define CFAM_ENGINE_CONFIG TO_REG(0x04)27 #define CFAM_CONFIG_CHIP_ID TO_REG(0x00)87 switch (TO_REG(addr)) { in fsi_cfam_config_write()
22 #define TO_REG(offset) ((offset) >> 2) macro100 val = s->regs[TO_REG(addr)]; in aspeed_pcie_rc_read()127 s->regs[TO_REG(addr)] = data; in aspeed_pcie_rc_write()131 s->regs[TO_REG(addr)] &= ~data; in aspeed_pcie_rc_write()343 val = s->regs[TO_REG(addr)]; in aspeed_pcie_cfg_read()348 val = s->regs[TO_REG(addr)]; in aspeed_pcie_cfg_read()488 rc->regs[TO_REG(reg)] |= BIT(data % 32); in aspeed_pcie_cfg_msi_notify()511 s->regs[TO_REG(addr)] = data; in aspeed_pcie_cfg_write()653 val = s->regs[TO_REG(addr)]; in aspeed_pcie_phy_read()685 s->regs[TO_REG(addr)] = data; in aspeed_pcie_phy_write()[all …]
42 #define TO_REG(addr) (addr >> 2) macro44 #define ENGINE_CONTROL TO_REG(0x00)45 #define INTERRUPT_CONTROL TO_REG(0x04)46 #define VGA_DETECT_CONTROL TO_REG(0x08)47 #define CLOCK_CONTROL TO_REG(0x0C)48 #define DATA_CHANNEL_1_AND_0 TO_REG(0x10)49 #define DATA_CHANNEL_7_AND_6 TO_REG(0x1C)50 #define DATA_CHANNEL_9_AND_8 TO_REG(0x20)51 #define DATA_CHANNEL_15_AND_14 TO_REG(0x2C)111 int reg = TO_REG(addr); in aspeed_adc_engine_read()[all …]
34 #define TO_REG(addr) ((addr) / sizeof(uint32_t)) macro56 val = sdhci->regs[TO_REG(addr)]; in aspeed_sdhci_read()79 sdhci->regs[TO_REG(addr)] = (uint32_t)val & ~ASPEED_SDHCI_INFO_RESET; in aspeed_sdhci_write()95 sdhci->regs[TO_REG(addr)] = (uint32_t)val; in aspeed_sdhci_write()117 sdhci->regs[TO_REG(ASPEED_SDHCI_IRQ_STAT)] |= BIT(n); in aspeed_sdhci_set_irq()121 sdhci->regs[TO_REG(ASPEED_SDHCI_IRQ_STAT)] &= ~BIT(n); in aspeed_sdhci_set_irq()170 sdhci->regs[TO_REG(ASPEED_SDHCI_INFO)] = ASPEED_SDHCI_INFO_SLOT0; in aspeed_sdhci_reset()172 sdhci->regs[TO_REG(ASPEED_SDHCI_INFO)] |= ASPEED_SDHCI_INFO_SLOT1; in aspeed_sdhci_reset()174 sdhci->regs[TO_REG(ASPEED_SDHCI_DEBOUNCE)] = ASPEED_SDHCI_DEBOUNCE_RESET; in aspeed_sdhci_reset()
49 #define TO_REG(addr) ((addr) / sizeof(uint32_t)) macro64 s->regs[TO_REG(CADENCE_SDHCI_HRS00)] = CADENCE_SDHCI_HRS00_POR_VAL; in cadence_sdhci_reset()74 val = s->regs[TO_REG(addr)]; in cadence_sdhci_read()107 s->regs[TO_REG(addr)] = val32; in cadence_sdhci_write()114 s->regs[TO_REG(addr)] = val32; in cadence_sdhci_write()117 s->regs[TO_REG(addr)] = val32; in cadence_sdhci_write()