Searched refs:TO_REG (Results 1 – 10 of 10) sorted by relevance
17 #define TO_REG(x) ((x) >> 2) macro19 #define FSI_MENP0 TO_REG(0x010)20 #define FSI_MENP32 TO_REG(0x014)21 #define FSI_MSENP0 TO_REG(0x018)22 #define FSI_MLEVP0 TO_REG(0x018)23 #define FSI_MSENP32 TO_REG(0x01c)24 #define FSI_MLEVP32 TO_REG(0x01c)25 #define FSI_MCENP0 TO_REG(0x020)26 #define FSI_MREFP0 TO_REG(0x020)27 #define FSI_MCENP32 TO_REG(0x024)[all …]
18 #define TO_REG(x) (x >> 2) macro20 #define APB2OPB_VERSION TO_REG(0x00)21 #define APB2OPB_TRIGGER TO_REG(0x04)23 #define APB2OPB_CONTROL TO_REG(0x08)26 #define APB2OPB_OPB2FSI TO_REG(0x0c)29 #define APB2OPB_OPB0_SEL TO_REG(0x10)30 #define APB2OPB_OPB1_SEL TO_REG(0x28)33 #define APB2OPB_OPB0_MODE TO_REG(0x14)34 #define APB2OPB_OPB1_MODE TO_REG(0x2c)37 #define APB2OPB_OPB0_XFER TO_REG(0x18)[all …]
32 #define TO_REG(x) ((x) >> 2) macro34 #define CFAM_CONFIG_CHIP_ID TO_REG(0x00)35 #define CFAM_CONFIG_PEEK_STATUS TO_REG(0x04)70 switch (TO_REG(addr)) { in fsi_cfam_config_write()
14 #define TO_REG(x) ((x) >> 2) macro25 int reg = TO_REG(addr); in fsi_slave_read()43 int reg = TO_REG(addr); in fsi_slave_write()
15 #define TO_REG(offset) ((offset) >> 2) macro41 int reg = TO_REG(addr); in fsi_scratchpad_read()61 int reg = TO_REG(addr); in fsi_scratchpad_write()
20 #define TO_REG(offset) ((offset) >> 2) macro22 #define HICR0 TO_REG(0x00)26 #define HICR1 TO_REG(0x04)27 #define HICR2 TO_REG(0x08)31 #define HICR3 TO_REG(0x0C)32 #define HICR4 TO_REG(0x10)34 #define IDR1 TO_REG(0x24)35 #define IDR2 TO_REG(0x28)36 #define IDR3 TO_REG(0x2C)37 #define ODR1 TO_REG(0x30)[all …]
26 #define TO_REG(o) (o >> 2) macro179 if ((ibt->regs[TO_REG(BT_CTRL)] & BT_CTRL_H2B_ATN) && in aspeed_ibt_update_irq()180 ((ibt->regs[TO_REG(BT_CR1)] & BT_CR1_IRQ_H2B) == BT_CR1_IRQ_H2B)) { in aspeed_ibt_update_irq()181 ibt->regs[TO_REG(BT_CR2)] |= BT_CR2_IRQ_H2B; in aspeed_ibt_update_irq()192 if ((ibt->regs[TO_REG(BT_CTRL)] & BT_CTRL_H_BUSY) && in aspeed_ibt_update_irq()193 ((ibt->regs[TO_REG(BT_CR1)] & BT_CR1_IRQ_HBUSY) == BT_CR1_IRQ_HBUSY)) { in aspeed_ibt_update_irq()194 ibt->regs[TO_REG(BT_CR2)] |= BT_CR2_IRQ_HBUSY; in aspeed_ibt_update_irq()279 ibt->regs[TO_REG(BT_CTRL)] |= BT_CTRL_H2B_ATN; in vm_handle_char()360 return !ibt->recv_waiting && !(ibt->regs[TO_REG(BT_CTRL)] & BT_CTRL_B_BUSY); in aspeed_ibt_chr_can_receive()406 ibt->regs[TO_REG(BT_CTRL)] &= ~BT_CTRL_H2B_ATN; in aspeed_ibt_write()[all …]
19 #define TO_REG(addr) ((addr) >> 2) macro24 int reg = TO_REG(addr); in aspeed_sli_read()41 int reg = TO_REG(addr); in aspeed_sli_write()57 int reg = TO_REG(addr); in aspeed_sliio_read()74 int reg = TO_REG(addr); in aspeed_sliio_write()
42 #define TO_REG(addr) (addr >> 2) macro44 #define ENGINE_CONTROL TO_REG(0x00)45 #define INTERRUPT_CONTROL TO_REG(0x04)46 #define VGA_DETECT_CONTROL TO_REG(0x08)47 #define CLOCK_CONTROL TO_REG(0x0C)48 #define DATA_CHANNEL_1_AND_0 TO_REG(0x10)49 #define DATA_CHANNEL_7_AND_6 TO_REG(0x1C)50 #define DATA_CHANNEL_9_AND_8 TO_REG(0x20)51 #define DATA_CHANNEL_15_AND_14 TO_REG(0x2C)52 #define BOUNDS_CHANNEL_0 TO_REG(0x30)[all …]
49 #define TO_REG(addr) ((addr) / sizeof(uint32_t)) macro64 s->regs[TO_REG(CADENCE_SDHCI_HRS00)] = CADENCE_SDHCI_HRS00_POR_VAL; in cadence_sdhci_reset()74 val = s->regs[TO_REG(addr)]; in cadence_sdhci_read()107 s->regs[TO_REG(addr)] = val32; in cadence_sdhci_write()114 s->regs[TO_REG(addr)] = val32; in cadence_sdhci_write()117 s->regs[TO_REG(addr)] = val32; in cadence_sdhci_write()