Lines Matching refs:TO_REG
42 #define TO_REG(addr) (addr >> 2) macro
44 #define ENGINE_CONTROL TO_REG(0x00)
45 #define INTERRUPT_CONTROL TO_REG(0x04)
46 #define VGA_DETECT_CONTROL TO_REG(0x08)
47 #define CLOCK_CONTROL TO_REG(0x0C)
48 #define DATA_CHANNEL_1_AND_0 TO_REG(0x10)
49 #define DATA_CHANNEL_7_AND_6 TO_REG(0x1C)
50 #define DATA_CHANNEL_9_AND_8 TO_REG(0x20)
51 #define DATA_CHANNEL_15_AND_14 TO_REG(0x2C)
52 #define BOUNDS_CHANNEL_0 TO_REG(0x30)
53 #define BOUNDS_CHANNEL_7 TO_REG(0x4C)
54 #define BOUNDS_CHANNEL_8 TO_REG(0x50)
55 #define BOUNDS_CHANNEL_15 TO_REG(0x6C)
56 #define HYSTERESIS_CHANNEL_0 TO_REG(0x70)
57 #define HYSTERESIS_CHANNEL_7 TO_REG(0x8C)
58 #define HYSTERESIS_CHANNEL_8 TO_REG(0x90)
59 #define HYSTERESIS_CHANNEL_15 TO_REG(0xAC)
60 #define INTERRUPT_SOURCE TO_REG(0xC0)
61 #define COMPENSATING_AND_TRIMMING TO_REG(0xC4)
111 int reg = TO_REG(addr); in aspeed_adc_engine_read()
171 int reg = TO_REG(addr); in aspeed_adc_engine_write()