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Searched refs:TM_QW1_OS (Results 1 – 8 of 8) sorted by relevance

/openbmc/qemu/hw/intc/
H A Dxive.c44 case TM_QW1_OS: in exception_mask()
58 case TM_QW1_OS: in xive_tctx_output()
102 case TM_QW1_OS: in xive_tctx_notify()
126 qemu_irq_lower(xive_tctx_output(tctx, TM_QW1_OS)); in xive_tctx_reset_os_signal()
336 return xive_tctx_accept(tctx, TM_QW1_OS); in xive_tm_ack_os_reg()
439 xive_tctx_ipb_update(tctx, TM_QW1_OS, ipb); in xive_tctx_need_resend()
712 tctx->regs[TM_QW1_OS + TM_LSMFB] = 0xFF; in xive_tctx_reset()
713 tctx->regs[TM_QW1_OS + TM_ACK_CNT] = 0xFF; in xive_tctx_reset()
714 tctx->regs[TM_QW1_OS + TM_AGE] = 0xFF; in xive_tctx_reset()
720 tctx->regs[TM_QW1_OS + TM_PIPR] = in xive_tctx_reset()
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H A Dxive2.c191 uint8_t *regs = &tctx->regs[TM_QW1_OS]; in xive2_tctx_save_os_ctx()
249 uint32_t qw1w2 = xive_tctx_word2(&tctx->regs[TM_QW1_OS]); in xive2_tm_pull_os_ctx()
266 memcpy(&tctx->regs[TM_QW1_OS + TM_WORD2], &qw1w2_new, 4); in xive2_tm_pull_os_ctx()
294 tctx->regs[TM_QW1_OS + TM_CPPR] = cppr; in xive2_tctx_restore_os_ctx()
356 xive_tctx_ipb_update(tctx, TM_QW1_OS, ipb); in xive2_tctx_need_resend()
375 memcpy(&tctx->regs[TM_QW1_OS + TM_WORD2], &qw1w2, 4); in xive2_tm_push_os_ctx()
484 uint32_t qw1w2 = xive_tctx_word2(&tctx->regs[TM_QW1_OS]); in xive2_presenter_tctx_match()
520 return TM_QW1_OS; in xive2_presenter_tctx_match()
H A Dspapr_xive_kvm.c86 state[0] = *((uint64_t *) &tctx->regs[TM_QW1_OS]); in kvmppc_xive_cpu_set_state()
116 *((uint64_t *) &tctx->regs[TM_QW1_OS]) = state[0]; in kvmppc_xive_cpu_get_state()
H A Dspapr_xive.c658 memcpy(&tctx->regs[TM_QW1_OS + TM_WORD2], &qw1w2, 4); in xive_tctx_set_os_cam()
/openbmc/linux/arch/powerpc/include/asm/
H A Dxive-regs.h58 #define TM_QW1_OS 0x010 /* Ring 0..2 */ macro
/openbmc/linux/arch/powerpc/sysdev/xive/
H A Dspapr.c650 in_be32(xive_tima + TM_QW1_OS + TM_WORD0), in xive_spapr_setup_cpu()
651 in_be32(xive_tima + TM_QW1_OS + TM_WORD1), in xive_spapr_setup_cpu()
652 in_be32(xive_tima + TM_QW1_OS + TM_WORD2)); in xive_spapr_setup_cpu()
876 if (!xive_core_init(np, &xive_spapr_ops, tima, TM_QW1_OS, max_prio)) in xive_spapr_init()
/openbmc/linux/arch/powerpc/kvm/
H A Dbook3s_xive.c281 __raw_writeb(xc->cppr, xive_tima + TM_QW1_OS + TM_CPPR); in xive_vm_scan_interrupts()
357 __be64 qw1 = __raw_readq(xive_tima + TM_QW1_OS); in xive_vm_h_ipoll()
510 __raw_writeb(cppr, xive_tima + TM_QW1_OS + TM_CPPR); in xive_vm_h_cppr()
615 __raw_writeb(xc->cppr, xive_tima + TM_QW1_OS + TM_CPPR); in xive_vm_h_eoi()
701 __raw_writeq(vcpu->arch.xive_saved_state.w01, tima + TM_QW1_OS); in kvmppc_xive_push_vcpu()
702 __raw_writel(vcpu->arch.xive_cam_word, tima + TM_QW1_OS + TM_WORD2); in kvmppc_xive_push_vcpu()
774 vcpu->arch.xive_saved_state.w01 = __raw_readq(tima + TM_QW1_OS); in kvmppc_xive_pull_vcpu()
/openbmc/qemu/include/hw/ppc/
H A Dxive_regs.h69 #define TM_QW1_OS 0x010 /* Ring 0..2 */ macro