Home
last modified time | relevance | path

Searched refs:TMIO_SD_CLKCTL (Results 1 – 3 of 3) sorted by relevance

/openbmc/u-boot/drivers/mmc/
H A Drenesas-sdhi.c51 reg = tmio_sd_readl(priv, TMIO_SD_CLKCTL); in renesas_sdhi_init_tuning()
53 tmio_sd_writel(priv, reg, TMIO_SD_CLKCTL); in renesas_sdhi_init_tuning()
71 reg = tmio_sd_readl(priv, TMIO_SD_CLKCTL); in renesas_sdhi_init_tuning()
73 tmio_sd_writel(priv, reg, TMIO_SD_CLKCTL); in renesas_sdhi_init_tuning()
86 reg = tmio_sd_readl(priv, TMIO_SD_CLKCTL); in renesas_sdhi_reset_tuning()
88 tmio_sd_writel(priv, reg, TMIO_SD_CLKCTL); in renesas_sdhi_reset_tuning()
99 reg = tmio_sd_readl(priv, TMIO_SD_CLKCTL); in renesas_sdhi_reset_tuning()
101 tmio_sd_writel(priv, reg, TMIO_SD_CLKCTL); in renesas_sdhi_reset_tuning()
359 tmp = tmio_sd_readl(priv, TMIO_SD_CLKCTL); in renesas_sdhi_set_ios()
361 tmio_sd_writel(priv, tmp, TMIO_SD_CLKCTL); in renesas_sdhi_set_ios()
H A Dtmio-common.h53 #define TMIO_SD_CLKCTL 0x048 /* clock divisor */ macro
H A Dtmio-common.c604 tmp = tmio_sd_readl(priv, TMIO_SD_CLKCTL); in tmio_sd_set_clk_rate()
613 tmio_sd_writel(priv, tmp, TMIO_SD_CLKCTL); in tmio_sd_set_clk_rate()
629 tmio_sd_writel(priv, tmp, TMIO_SD_CLKCTL); in tmio_sd_set_clk_rate()