Searched refs:TEGRA234_CLK_PLLA_OUT0 (Results 1 – 2 of 2) sorted by relevance
209 #define TEGRA234_CLK_PLLA_OUT0 104U macro
199 assigned-clock-parents = <&bpmp TEGRA234_CLK_PLLA_OUT0>;213 assigned-clock-parents = <&bpmp TEGRA234_CLK_PLLA_OUT0>;227 assigned-clock-parents = <&bpmp TEGRA234_CLK_PLLA_OUT0>;241 assigned-clock-parents = <&bpmp TEGRA234_CLK_PLLA_OUT0>;255 assigned-clock-parents = <&bpmp TEGRA234_CLK_PLLA_OUT0>;269 assigned-clock-parents = <&bpmp TEGRA234_CLK_PLLA_OUT0>;379 assigned-clock-parents = <&bpmp TEGRA234_CLK_PLLA_OUT0>;392 assigned-clock-parents = <&bpmp TEGRA234_CLK_PLLA_OUT0>;3583 <&bpmp TEGRA234_CLK_PLLA_OUT0>;3586 <&bpmp TEGRA234_CLK_PLLA_OUT0>,[all …]