Lines Matching refs:TEGRA234_CLK_PLLA_OUT0

199 					assigned-clock-parents = <&bpmp TEGRA234_CLK_PLLA_OUT0>;
213 					assigned-clock-parents = <&bpmp TEGRA234_CLK_PLLA_OUT0>;
227 					assigned-clock-parents = <&bpmp TEGRA234_CLK_PLLA_OUT0>;
241 					assigned-clock-parents = <&bpmp TEGRA234_CLK_PLLA_OUT0>;
255 					assigned-clock-parents = <&bpmp TEGRA234_CLK_PLLA_OUT0>;
269 					assigned-clock-parents = <&bpmp TEGRA234_CLK_PLLA_OUT0>;
379 					assigned-clock-parents = <&bpmp TEGRA234_CLK_PLLA_OUT0>;
392 					assigned-clock-parents = <&bpmp TEGRA234_CLK_PLLA_OUT0>;
405 					assigned-clock-parents = <&bpmp TEGRA234_CLK_PLLA_OUT0>;
418 					assigned-clock-parents = <&bpmp TEGRA234_CLK_PLLA_OUT0>;
431 					assigned-clock-parents = <&bpmp TEGRA234_CLK_PLLA_OUT0>;
444 					assigned-clock-parents = <&bpmp TEGRA234_CLK_PLLA_OUT0>;
3583 			 <&bpmp TEGRA234_CLK_PLLA_OUT0>;
3586 				  <&bpmp TEGRA234_CLK_PLLA_OUT0>,
3590 					 <&bpmp TEGRA234_CLK_PLLA_OUT0>;