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Searched refs:TCG_REG_TMP0 (Results 1 – 5 of 5) sorted by relevance

/openbmc/qemu/tcg/loongarch64/
H A Dtcg-target.c.inc469 tcg_out_movi(s, type, TCG_REG_TMP0, imm);
471 tcg_out_opc_add_w(s, rd, rs, TCG_REG_TMP0);
473 tcg_out_opc_add_d(s, rd, rs, TCG_REG_TMP0);
554 tcg_out_opc_maskeqz(s, TCG_REG_TMP0, TCG_REG_TMP0, a1);
556 tcg_out_opc_or(s, a0, TCG_REG_TMP0, a0);
642 arg2 = TCG_REG_TMP0;
932 .ntmp = 1, .tmp = { TCG_REG_TMP0 }
1069 h->base = TCG_REG_TMP0;
1196 base = TCG_REG_TMP0;
1249 tcg_out_ld(s, TCG_TYPE_PTR, TCG_REG_TMP0, TCG_REG_TMP0, 0);
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H A Dtcg-target.h84 TCG_REG_TMP0 = TCG_REG_T8, enumerator
/openbmc/qemu/tcg/riscv/
H A Dtcg-target.c.inc762 tcg_out_opc_reg(s, OPC_SLTU, TCG_REG_TMP0,
848 arg2 = TCG_REG_TMP0;
1266 addr_adj = TCG_REG_TMP0;
1294 tcg_out_opc_reg(s, OPC_ADD_UW, TCG_REG_TMP0,
1297 tcg_out_ext32u(s, TCG_REG_TMP0, addr_reg);
1298 tcg_out_opc_reg(s, OPC_ADD, TCG_REG_TMP0,
1299 TCG_REG_TMP0, TCG_REG_TMP2);
1301 *pbase = TCG_REG_TMP0;
1320 base = TCG_REG_TMP0;
1334 base = TCG_REG_TMP0;
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H A Dtcg-target.h71 TCG_REG_TMP0 = TCG_REG_T6, enumerator
/openbmc/qemu/tcg/aarch64/
H A Dtcg-target.c.inc75 #define TCG_REG_TMP0 TCG_REG_X16
1056 TCGReg temp = TCG_REG_TMP0;
1420 tcg_out_insn(s, 3207, BLR, TCG_REG_TMP0);
1603 rl = TCG_REG_TMP0;
1620 al = TCG_REG_TMP0;
1661 a1 = TCG_REG_TMP0;
1700 .ntmp = 1, .tmp = { TCG_REG_TMP0 }
1780 TCG_REG_TMP0, TCG_REG_TMP0, addr_reg,
2007 ll = TCG_REG_TMP0;
2065 tcg_out_insn(s, 3207, BR, TCG_REG_TMP0);
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