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Searched refs:TCG_GUEST_DEFAULT_MO (Results 1 – 18 of 18) sorted by relevance

/openbmc/qemu/accel/tcg/
H A Dinternal-target.h111 #ifdef TCG_GUEST_DEFAULT_MO
113 ((type) & TCG_GUEST_DEFAULT_MO & ~TCG_TARGET_DEFAULT_MO)
H A Dtcg-all.c77 # ifndef TCG_GUEST_DEFAULT_MO in DECLARE_INSTANCE_CHECKER()
H A Dtranslate-all.c348 #ifdef TCG_GUEST_DEFAULT_MO in tb_gen_code()
349 tcg_ctx->guest_mo = TCG_GUEST_DEFAULT_MO; in tb_gen_code()
/openbmc/qemu/target/avr/
H A Dcpu.h33 #define TCG_GUEST_DEFAULT_MO 0 macro
/openbmc/qemu/target/microblaze/
H A Dcpu.h28 #define TCG_GUEST_DEFAULT_MO TCG_MO_ALL macro
/openbmc/qemu/target/openrisc/
H A Dcpu.h27 #define TCG_GUEST_DEFAULT_MO (0) macro
/openbmc/qemu/target/hppa/
H A Dcpu.h32 #define TCG_GUEST_DEFAULT_MO TCG_MO_ALL macro
/openbmc/qemu/target/alpha/
H A Dcpu.h28 #define TCG_GUEST_DEFAULT_MO (0) macro
/openbmc/qemu/target/loongarch/
H A Dcpu.h42 #define TCG_GUEST_DEFAULT_MO (0) macro
/openbmc/qemu/target/xtensa/
H A Dcpu.h38 #define TCG_GUEST_DEFAULT_MO (0) macro
/openbmc/qemu/target/s390x/
H A Dcpu.h37 #define TCG_GUEST_DEFAULT_MO (TCG_MO_ALL & ~TCG_MO_ST_LD) macro
/openbmc/qemu/target/riscv/
H A Dcpu.h45 #define TCG_GUEST_DEFAULT_MO 0 macro
/openbmc/qemu/target/sparc/
H A Dcpu.h30 #define TCG_GUEST_DEFAULT_MO (TCG_MO_LD_LD | TCG_MO_LD_ST | TCG_MO_ST_ST) macro
/openbmc/qemu/target/mips/
H A Dcpu.h13 #define TCG_GUEST_DEFAULT_MO (0) macro
/openbmc/qemu/docs/devel/
H A Dmulti-thread-tcg.rst29 guest (TCG_GUEST_DEFAULT_MO & ~TCG_TARGET_DEFAULT_MO is zero) and the
/openbmc/qemu/target/i386/
H A Dcpu.h34 #define TCG_GUEST_DEFAULT_MO (TCG_MO_ALL & ~TCG_MO_ST_LD) macro
/openbmc/qemu/target/ppc/
H A Dcpu.h32 #define TCG_GUEST_DEFAULT_MO 0 macro
/openbmc/qemu/target/arm/
H A Dcpu.h31 #define TCG_GUEST_DEFAULT_MO (0) macro