174433bf0SRichard Henderson /* 274433bf0SRichard Henderson * PA-RISC cpu parameters for qemu. 374433bf0SRichard Henderson * 474433bf0SRichard Henderson * Copyright (c) 2016 Richard Henderson <rth@twiddle.net> 574433bf0SRichard Henderson * SPDX-License-Identifier: LGPL-2.0+ 674433bf0SRichard Henderson */ 774433bf0SRichard Henderson 874433bf0SRichard Henderson #ifndef HPPA_CPU_PARAM_H 94f31b54bSMarkus Armbruster #define HPPA_CPU_PARAM_H 1074433bf0SRichard Henderson 1174433bf0SRichard Henderson #define TARGET_LONG_BITS 64 1208db1785SRichard Henderson 1308db1785SRichard Henderson #if defined(CONFIG_USER_ONLY) && defined(TARGET_ABI32) 1408db1785SRichard Henderson # define TARGET_PHYS_ADDR_SPACE_BITS 32 1574433bf0SRichard Henderson # define TARGET_VIRT_ADDR_SPACE_BITS 32 1674433bf0SRichard Henderson #else 17fa71b4f8SRichard Henderson /* ??? PA-8000 through 8600 have 40 bits; PA-8700 and 8900 have 44 bits. */ 18fa71b4f8SRichard Henderson # define TARGET_PHYS_ADDR_SPACE_BITS 40 1974433bf0SRichard Henderson # define TARGET_VIRT_ADDR_SPACE_BITS 64 2074433bf0SRichard Henderson #endif 2108db1785SRichard Henderson 2274433bf0SRichard Henderson #define TARGET_PAGE_BITS 12 2374433bf0SRichard Henderson 24*e92dd332SPhilippe Mathieu-Daudé /* PA-RISC 1.x processors have a strong memory model. */ 25*e92dd332SPhilippe Mathieu-Daudé /* 26*e92dd332SPhilippe Mathieu-Daudé * ??? While we do not yet implement PA-RISC 2.0, those processors have 27*e92dd332SPhilippe Mathieu-Daudé * a weak memory model, but with TLB bits that force ordering on a per-page 28*e92dd332SPhilippe Mathieu-Daudé * basis. It's probably easier to fall back to a strong memory model. 29*e92dd332SPhilippe Mathieu-Daudé */ 30*e92dd332SPhilippe Mathieu-Daudé #define TCG_GUEST_DEFAULT_MO TCG_MO_ALL 31*e92dd332SPhilippe Mathieu-Daudé 3274433bf0SRichard Henderson #endif 33