/openbmc/qemu/target/ppc/ |
H A D | mmu_common.c | 43 qemu_log_mask(CPU_LOG_MMU, "%s: " TARGET_FMT_lx "\n", __func__, value); in ppc_store_sdr1() 51 qemu_log_mask(LOG_GUEST_ERROR, "Invalid bits 0x"TARGET_FMT_lx in ppc_store_sdr1() 56 qemu_log_mask(LOG_GUEST_ERROR, "Invalid HTABSIZE 0x" TARGET_FMT_lx in ppc_store_sdr1() 106 qemu_log_mask(CPU_LOG_MMU, "TLB %d/%d %s [" TARGET_FMT_lx in ppc6xx_tlb_check() 107 " " TARGET_FMT_lx "] <> " TARGET_FMT_lx "\n", in ppc6xx_tlb_check() 113 qemu_log_mask(CPU_LOG_MMU, "TLB %d/%d %s " TARGET_FMT_lx " <> " in ppc6xx_tlb_check() 114 TARGET_FMT_lx " " TARGET_FMT_lx " %c %c\n", in ppc6xx_tlb_check() 199 qemu_log_mask(CPU_LOG_MMU, "%s: %cBAT v " TARGET_FMT_lx "\n", __func__, in get_bat_6xx_tlb() 213 qemu_log_mask(CPU_LOG_MMU, "%s: %cBAT%d v " TARGET_FMT_lx " BATu " in get_bat_6xx_tlb() 214 TARGET_FMT_lx " BATl " TARGET_FMT_lx "\n", __func__, in get_bat_6xx_tlb() [all …]
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H A D | mmu_helper.c | 73 TARGET_FMT_lx "\n", nr, env->nb_tlb, eaddr); in ppc6xx_tlb_invalidate_virt2() 98 qemu_log_mask(CPU_LOG_MMU, "Set TLB %d/%d EPN " TARGET_FMT_lx " PTE0 " in ppc6xx_tlb_store() 99 TARGET_FMT_lx " PTE1 " TARGET_FMT_lx "\n", nr, env->nb_tlb, in ppc6xx_tlb_store() 163 qemu_log_mask(CPU_LOG_MMU, "Flush BAT from " TARGET_FMT_lx in do_invalidate_BAT() 164 " to " TARGET_FMT_lx " (" TARGET_FMT_lx ")\n", in do_invalidate_BAT() 176 qemu_log_mask(CPU_LOG_MMU, "Set %cBAT%d%c to " TARGET_FMT_lx " (" in dump_store_bat() 177 TARGET_FMT_lx ")\n", ID, nr, ul == 0 ? 'u' : 'l', in dump_store_bat() 344 "%s: reg=%d " TARGET_FMT_lx " " TARGET_FMT_lx "\n", __func__, in helper_store_sr() 438 "%s: local=%d addr=" TARGET_FMT_lx " ric=%u prs=%d r=%d is=%u\n", in helper_tlbie_isa300() 574 qemu_log_mask(CPU_LOG_MMU, "%s: EPN " TARGET_FMT_lx " " TARGET_FMT_lx in do_6xx_tlb() [all …]
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H A D | mmu-hash32.c | 60 LOG_BATS("%s: %cBAT v " TARGET_FMT_lx "\n", __func__, in ppc_hash32_bat_lookup() 75 LOG_BATS("%s: %cBAT%d v " TARGET_FMT_lx " BATu " TARGET_FMT_lx in ppc_hash32_bat_lookup() 76 " BATl " TARGET_FMT_lx "\n", __func__, in ppc_hash32_bat_lookup() 94 LOG_BATS("no BAT match for " TARGET_FMT_lx ":\n", ea); in ppc_hash32_bat_lookup() 101 LOG_BATS("%s: %cBAT%d v " TARGET_FMT_lx " BATu " TARGET_FMT_lx in ppc_hash32_bat_lookup() 102 " BATl " TARGET_FMT_lx "\n\t" TARGET_FMT_lx " " in ppc_hash32_bat_lookup() 103 TARGET_FMT_lx " " TARGET_FMT_lx "\n", in ppc_hash32_bat_lookup()
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H A D | misc_helper.c | 36 qemu_log("Read SPR %d %03x => " TARGET_FMT_lx "\n", sprn, sprn, in helper_load_dump_spr() 42 qemu_log("Write SPR %d %03x <= " TARGET_FMT_lx "\n", sprn, sprn, in helper_store_dump_spr() 180 qemu_log_mask(CPU_LOG_MMU, "%s: " TARGET_FMT_lx "\n", __func__, val); in helper_store_ptcr() 186 error_report("Invalid bits 0x"TARGET_FMT_lx" set in PTCR", in helper_store_ptcr() 192 error_report("Invalid Partition Table size 0x" TARGET_FMT_lx in helper_store_ptcr() 308 TARGET_FMT_lx"\n", val); in helper_store_sprc() 347 TARGET_FMT_lx"\n", sprc); in helper_load_sprd() 370 qemu_log("SPRD write 0x" TARGET_FMT_lx " to SCRATCH%d\n", val, nr); in helper_store_sprd() 375 TARGET_FMT_lx"\n", sprc); in helper_store_sprd()
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H A D | mmu-booke.c | 39 qemu_log_mask(CPU_LOG_MMU, "%s: TLB %d address " TARGET_FMT_lx in ppcemb_tlb_check() 40 " PID %u <=> " TARGET_FMT_lx " " TARGET_FMT_lx " %u %x\n", in ppcemb_tlb_check() 126 qemu_log_mask(CPU_LOG_MMU, "%s: access %s " TARGET_FMT_lx " => " in mmu40x_get_physical_address() 204 "%s: access %s " TARGET_FMT_lx " => " HWADDR_FMT_plx in mmubooke_get_physical_address() 237 qemu_log_mask(CPU_LOG_MMU, "%s: TLB ADDR=0x" TARGET_FMT_lx in ppcmas_tlb_check() 342 "0x" TARGET_FMT_lx "\n", __func__, address); in mmubooke206_check_tlb() 415 qemu_log_mask(CPU_LOG_MMU, "%s: access %s " TARGET_FMT_lx " => " in mmubooke206_get_physical_address()
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H A D | cpu_init.c | 2883 cpu_abort(env_cpu(env), "Unknown CPU: " TARGET_FMT_lx "\n", in init_proc_e500() 2908 cpu_abort(env_cpu(env), "Unknown CPU: " TARGET_FMT_lx "\n", in init_proc_e500() 7539 qemu_fprintf(f, "NIP " TARGET_FMT_lx " LR " TARGET_FMT_lx " CTR " in ppc_cpu_dump_state() 7540 TARGET_FMT_lx " XER " TARGET_FMT_lx " CPU#%d\n", in ppc_cpu_dump_state() 7543 qemu_fprintf(f, "MSR " TARGET_FMT_lx " HID0 " TARGET_FMT_lx " HF " in ppc_cpu_dump_state() 7581 qemu_fprintf(f, " ] RES %03x@" TARGET_FMT_lx "\n", in ppc_cpu_dump_state() 7594 qemu_fprintf(f, "FPSCR " TARGET_FMT_lx "\n", env->fpscr); in ppc_cpu_dump_state() 7598 qemu_fprintf(f, " SRR0 " TARGET_FMT_lx " SRR1 " TARGET_FMT_lx in ppc_cpu_dump_state() 7599 " PVR " TARGET_FMT_lx " VRSAVE " TARGET_FMT_lx "\n", in ppc_cpu_dump_state() 7603 qemu_fprintf(f, "SPRG0 " TARGET_FMT_lx " SPRG1 " TARGET_FMT_lx in ppc_cpu_dump_state() [all …]
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H A D | mmu-hash64.c | 59 LOG_SLB("%s: eaddr " TARGET_FMT_lx "\n", __func__, eaddr); in slb_lookup() 276 " esid 0x"TARGET_FMT_lx" vsid 0x"TARGET_FMT_lx, in ppc_store_slb() 285 LOG_SLB("%s: " TARGET_FMT_lu " " TARGET_FMT_lx " - " TARGET_FMT_lx in ppc_store_slb() 754 " vsid=" TARGET_FMT_lx " ptem=" TARGET_FMT_lx in ppc_hash64_htab_lookup() 765 " vsid=" TARGET_FMT_lx " api=" TARGET_FMT_lx in ppc_hash64_htab_lookup() 977 error_report("Bad VRMA page size encoding 0x" TARGET_FMT_lx, llp); in build_vrma_slbe()
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/openbmc/qemu/target/mips/tcg/sysemu/ |
H A D | special_helper.c | 48 qemu_log("ERET: PC " TARGET_FMT_lx " EPC " TARGET_FMT_lx, in debug_pre_eret() 51 qemu_log(" ErrorEPC " TARGET_FMT_lx, env->CP0_ErrorEPC); in debug_pre_eret() 54 qemu_log(" DEPC " TARGET_FMT_lx, env->CP0_DEPC); in debug_pre_eret() 63 qemu_log(" => PC " TARGET_FMT_lx " EPC " TARGET_FMT_lx, in debug_post_eret() 66 qemu_log(" ErrorEPC " TARGET_FMT_lx, env->CP0_ErrorEPC); in debug_post_eret() 69 qemu_log(" DEPC " TARGET_FMT_lx, env->CP0_DEPC); in debug_post_eret()
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/openbmc/qemu/target/loongarch/ |
H A D | cpu.c | 174 "%s enter: pc " TARGET_FMT_lx " ERA " TARGET_FMT_lx in loongarch_cpu_do_interrupt() 175 " TLBRERA " TARGET_FMT_lx " exception: %d (%s)\n", in loongarch_cpu_do_interrupt() 274 "%s: PC " TARGET_FMT_lx " ERA " TARGET_FMT_lx in loongarch_cpu_do_interrupt() 275 " cause %d\n" " A " TARGET_FMT_lx " D " in loongarch_cpu_do_interrupt() 276 TARGET_FMT_lx " vector = %d ExC " TARGET_FMT_lx "ExS" in loongarch_cpu_do_interrupt() 277 TARGET_FMT_lx "\n", in loongarch_cpu_do_interrupt() 288 "%s: PC " TARGET_FMT_lx " ERA " TARGET_FMT_lx in loongarch_cpu_do_interrupt() 289 " cause %d%s\n, ESTAT " TARGET_FMT_lx in loongarch_cpu_do_interrupt() 290 " EXCFG " TARGET_FMT_lx " BADVA " TARGET_FMT_lx in loongarch_cpu_do_interrupt() 291 "BADI " TARGET_FMT_lx " SYS_NUM " TARGET_FMT_lu in loongarch_cpu_do_interrupt() [all …]
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/openbmc/qemu/include/exec/ |
H A D | target_long.h | 29 #define TARGET_FMT_lx "%08x" macro 36 #define TARGET_FMT_lx "%016" PRIx64 macro
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H A D | abi_ptr.h | 29 #define TARGET_ABI_FMT_ptr TARGET_FMT_lx
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/openbmc/qemu/target/sparc/ |
H A D | cpu.c | 585 qemu_printf(" %-20s (IU " TARGET_FMT_lx in sparc_cpu_list() 624 qemu_fprintf(f, "pc: " TARGET_FMT_lx " npc: " TARGET_FMT_lx "\n", env->pc, in sparc_cpu_dump_state() 631 qemu_fprintf(f, " " TARGET_FMT_lx, env->gregs[i]); in sparc_cpu_dump_state() 643 qemu_fprintf(f, TARGET_FMT_lx " ", env->regwptr[i + x * 8]); in sparc_cpu_dump_state() 670 qemu_fprintf(f, "tbr: " TARGET_FMT_lx " hpstate: " TARGET_FMT_lx " htba: " in sparc_cpu_dump_state() 671 TARGET_FMT_lx "\n", env->tbr, env->hpstate, env->htba); in sparc_cpu_dump_state() 676 qemu_fprintf(f, "fsr: " TARGET_FMT_lx " y: " TARGET_FMT_lx " fprs: %016x\n", in sparc_cpu_dump_state() 685 qemu_fprintf(f, "fsr: " TARGET_FMT_lx " y: " TARGET_FMT_lx "\n", in sparc_cpu_dump_state()
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H A D | mmu_helper.c | 230 HWADDR_FMT_plx ", vaddr " TARGET_FMT_lx "\n", in sparc_cpu_tlb_fill() 362 qemu_printf("VA: " TARGET_FMT_lx ", PA: " HWADDR_FMT_plx in dump_mmu() 363 " PDE: " TARGET_FMT_lx "\n", va, pa, pde); in dump_mmu() 368 qemu_printf(" VA: " TARGET_FMT_lx ", PA: " in dump_mmu() 369 HWADDR_FMT_plx " PDE: " TARGET_FMT_lx "\n", in dump_mmu() 375 qemu_printf(" VA: " TARGET_FMT_lx ", PA: " in dump_mmu() 377 TARGET_FMT_lx "\n", in dump_mmu()
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H A D | ldst_helper.c | 396 DPRINTF_ASI("%s "TARGET_FMT_lx " asi 0x%02x = %02" PRIx64 "\n", txt, in dump_asi() 400 DPRINTF_ASI("%s "TARGET_FMT_lx " asi 0x%02x = %04" PRIx64 "\n", txt, in dump_asi() 404 DPRINTF_ASI("%s "TARGET_FMT_lx " asi 0x%02x = %08" PRIx64 "\n", txt, in dump_asi() 408 DPRINTF_ASI("%s "TARGET_FMT_lx " asi 0x%02x = %016" PRIx64 "\n", txt, in dump_asi() 427 " asi 0x%02x from " TARGET_FMT_lx "\n", in sparc_raise_mmu_fault() 432 " from " TARGET_FMT_lx "\n", in sparc_raise_mmu_fault() 485 printf("Unassigned mem access to " HWADDR_FMT_plx " from " TARGET_FMT_lx in sparc_raise_mmu_fault()
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/openbmc/qemu/target/hexagon/ |
H A D | printinsn.c | 79 g_string_append_printf(buf, "0x" TARGET_FMT_lx "\t", words[i]); in snprint_a_pkt_disas() 101 g_string_append_printf(buf, "\n0x" TARGET_FMT_lx ": ", pc); in snprint_a_pkt_disas()
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H A D | op_helper.c | 57 HEX_DEBUG_LOG("log_store%d(0x" TARGET_FMT_lx in log_store32() 68 HEX_DEBUG_LOG("log_store%d(0x" TARGET_FMT_lx in log_store64() 79 HEX_DEBUG_LOG("Start packet: pc = 0x" TARGET_FMT_lx "\n", in HELPER() 182 HEX_DEBUG_LOG("\tmemb[0x" TARGET_FMT_lx "] = %" PRId32 in print_store() 187 HEX_DEBUG_LOG("\tmemh[0x" TARGET_FMT_lx "] = %" PRId32 in print_store() 192 HEX_DEBUG_LOG("\tmemw[0x" TARGET_FMT_lx "] = %" PRId32 in print_store() 196 HEX_DEBUG_LOG("\tmemd[0x" TARGET_FMT_lx "] = %" PRId64 in print_store() 216 HEX_DEBUG_LOG("Packet committed: pc = 0x" TARGET_FMT_lx "\n", this_PC); in HELPER() 225 HEX_DEBUG_LOG("\tr%d = " TARGET_FMT_ld " (0x" TARGET_FMT_lx ")\n", in HELPER() 236 HEX_DEBUG_LOG("\tp%d = 0x" TARGET_FMT_lx "\n", in HELPER() [all …]
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/openbmc/qemu/hw/ppc/ |
H A D | spapr_vio.c | 168 hcall_dprintf("Unit 0x" TARGET_FMT_lx " does not exist\n", reg); in h_reg_crq() 174 hcall_dprintf("Queue size too small or too big (0x" TARGET_FMT_lx in h_reg_crq() 181 hcall_dprintf("Queue not aligned (0x" TARGET_FMT_lx ")\n", queue_addr); in h_reg_crq() 222 hcall_dprintf("Unit 0x" TARGET_FMT_lx " does not exist\n", reg); in h_free_crq() 239 hcall_dprintf("Unit 0x" TARGET_FMT_lx " does not exist\n", reg); in h_send_crq() 259 hcall_dprintf("Unit 0x" TARGET_FMT_lx " does not exist\n", reg); in h_enable_crq()
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H A D | spapr_hcall.c | 265 qemu_log_mask(LOG_UNIMP, "h_page_init: Bad flags (" TARGET_FMT_lx "\n", in h_page_init() 936 qemu_log_mask(LOG_UNIMP, "Unimplemented SPAPR hcall 0x"TARGET_FMT_lx"%s\n", in h_clean_slb() 944 qemu_log_mask(LOG_UNIMP, "Unimplemented SPAPR hcall 0x"TARGET_FMT_lx"%s\n", in h_invalidate_pid() 1004 TARGET_FMT_lx" proc_tbl_size 0x"TARGET_FMT_lx"\n", in h_register_process_table() 1578 qemu_log_mask(LOG_UNIMP, "Unimplemented SPAPR hcall 0x" TARGET_FMT_lx "\n", in spapr_hypercall()
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/openbmc/qemu/target/mips/ |
H A D | cpu.c | 86 qemu_fprintf(f, "pc=0x" TARGET_FMT_lx " HI=0x" TARGET_FMT_lx in mips_cpu_dump_state() 87 " LO=0x" TARGET_FMT_lx " ds %04x " in mips_cpu_dump_state() 88 TARGET_FMT_lx " " TARGET_FMT_ld "\n", in mips_cpu_dump_state() 95 qemu_fprintf(f, " %s " TARGET_FMT_lx, in mips_cpu_dump_state() 103 TARGET_FMT_lx "\n", in mips_cpu_dump_state()
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/openbmc/qemu/target/alpha/ |
H A D | helper.c | 490 qemu_fprintf(f, "PC " TARGET_FMT_lx " PS %02x\n", in alpha_cpu_dump_state() 493 qemu_fprintf(f, "%-8s" TARGET_FMT_lx "%c", in alpha_cpu_dump_state() 498 qemu_fprintf(f, "lock_a " TARGET_FMT_lx " lock_v " TARGET_FMT_lx "\n", in alpha_cpu_dump_state()
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/openbmc/qemu/target/loongarch/tcg/ |
H A D | op_helper.c | 117 qemu_log_mask(CPU_LOG_INT, "%s: TLBRERA " TARGET_FMT_lx "\n", in helper_ertn() 124 qemu_log_mask(CPU_LOG_INT, "%s: ERA " TARGET_FMT_lx "\n", in helper_ertn()
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/openbmc/qemu/hw/intc/ |
H A D | spapr_xive.c | 955 qemu_log_mask(LOG_GUEST_ERROR, "XIVE: Unknown LISN " TARGET_FMT_lx "\n", in h_int_get_source_info() 961 qemu_log_mask(LOG_GUEST_ERROR, "XIVE: Invalid LISN " TARGET_FMT_lx "\n", in h_int_get_source_info() 1072 qemu_log_mask(LOG_GUEST_ERROR, "XIVE: Unknown LISN " TARGET_FMT_lx "\n", in h_int_set_source_config() 1079 qemu_log_mask(LOG_GUEST_ERROR, "XIVE: Invalid LISN " TARGET_FMT_lx "\n", in h_int_set_source_config() 1179 qemu_log_mask(LOG_GUEST_ERROR, "XIVE: Unknown LISN " TARGET_FMT_lx "\n", in h_int_get_source_config() 1186 qemu_log_mask(LOG_GUEST_ERROR, "XIVE: Invalid LISN " TARGET_FMT_lx "\n", in h_int_get_source_config() 1704 qemu_log_mask(LOG_GUEST_ERROR, "XIVE: Unknown LISN " TARGET_FMT_lx "\n", in h_int_esb() 1711 qemu_log_mask(LOG_GUEST_ERROR, "XIVE: Invalid LISN " TARGET_FMT_lx "\n", in h_int_esb() 1776 qemu_log_mask(LOG_GUEST_ERROR, "XIVE: Unknown LISN " TARGET_FMT_lx "\n", in h_int_sync() 1783 qemu_log_mask(LOG_GUEST_ERROR, "XIVE: Invalid LISN " TARGET_FMT_lx "\n", in h_int_sync()
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/openbmc/qemu/target/riscv/ |
H A D | monitor.c | 67 monitor_printf(mon, TARGET_FMT_lx " " HWADDR_FMT_plx " " TARGET_FMT_lx in print_pte()
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/openbmc/qemu/target/hppa/ |
H A D | helper.c | 133 qemu_fprintf(f, "IA_F %08" PRIx64 ":%0*" PRIx64 " (" TARGET_FMT_lx ")\n" in hppa_cpu_dump_state() 134 "IA_B %08" PRIx64 ":%0*" PRIx64 " (" TARGET_FMT_lx ")\n", in hppa_cpu_dump_state()
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/openbmc/qemu/include/user/ |
H A D | abitypes.h | 66 #define TARGET_ABI_FMT_lx TARGET_FMT_lx
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