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Searched refs:Ser1SDCR0 (Results 1 – 4 of 4) sorted by relevance

/openbmc/linux/arch/arm/mach-sa1100/
H A Dpm.c72 SAVE(Ser1SDCR0); in sa11x0_pm_enter()
106 RESTORE(Ser1SDCR0); in sa11x0_pm_enter()
H A Dassabet.c689 Ser1SDCR0 |= SDCR0_SUS; in assabet_map_io()
/openbmc/linux/arch/arm/mach-sa1100/include/mach/
H A DSA-1100.h429 #define Ser1SDCR0 __REG(0x80020060) /* Ser. port 1 SDLC Control Reg. 0 */ macro
/openbmc/u-boot/include/
H A DSA-1100.h653 #define Ser1SDCR0 /* Ser. port 1 SDLC Control Reg. 0 */ \ macro