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Searched refs:Ser0UDCCS0 (Results 1 – 2 of 2) sorted by relevance

/openbmc/linux/arch/arm/mach-sa1100/include/mach/
H A DSA-1100.h115 #define Ser0UDCCS0 __REG(0x80000010) /* Ser. port 0 UDC Control/Status reg. end-point 0 */ macro
/openbmc/u-boot/include/
H A DSA-1100.h245 #define Ser0UDCCS0 /* Ser. port 0 UDC Control/Status */ \ macro