Searched refs:SUNXI_DRAM_CTL0_BASE (Results 1 – 15 of 15) sorted by relevance
146 #define ZQnPR(x) (SUNXI_DRAM_CTL0_BASE + 0x00000144 + 0x10 * x)147 #define ZQnDR(x) (SUNXI_DRAM_CTL0_BASE + 0x00000148 + 0x10 * x)148 #define ZQnSR(x) (SUNXI_DRAM_CTL0_BASE + 0x0000014c + 0x10 * x)150 #define DXnGTR(x) (SUNXI_DRAM_CTL0_BASE + 0x00000340 + 0x80 * x)151 #define DXnGCR0(x) (SUNXI_DRAM_CTL0_BASE + 0x00000344 + 0x80 * x)152 #define DXnGSR0(x) (SUNXI_DRAM_CTL0_BASE + 0x00000348 + 0x80 * x)153 #define DXnGSR1(x) (SUNXI_DRAM_CTL0_BASE + 0x0000034c + 0x80 * x)154 #define DXnGSR2(x) (SUNXI_DRAM_CTL0_BASE + 0x00000350 + 0x80 * x)156 #define CAIOCR(x) (SUNXI_DRAM_CTL0_BASE + 0x00000210 + 0x4 * (x))157 #define DXnMDLR(x) (SUNXI_DRAM_CTL0_BASE + 0x00000300 + 0x80 * x)[all …]
145 #define DXnGTR(x) (SUNXI_DRAM_CTL0_BASE + 0x00000340 + 0x80 * x)146 #define DXnGCR0(x) (SUNXI_DRAM_CTL0_BASE + 0x00000344 + 0x80 * x)147 #define DXnGSR0(x) (SUNXI_DRAM_CTL0_BASE + 0x00000348 + 0x80 * x)148 #define DXnGSR1(x) (SUNXI_DRAM_CTL0_BASE + 0x0000034c + 0x80 * x)149 #define DXnGSR2(x) (SUNXI_DRAM_CTL0_BASE + 0x00000350 + 0x80 * x)
32 #define SUNXI_DRAM_CTL0_BASE 0x04003000 macro
45 #define SUNXI_DRAM_CTL0_BASE (REGS_AHB0_BASE + 0x63000) macro
156 #define SUNXI_DRAM_CTL0_BASE 0x01c63000 macro
89 (struct sunxi_mctl_ctl_reg *)SUNXI_DRAM_CTL0_BASE; in auto_set_timing_para()173 (struct sunxi_mctl_ctl_reg *)SUNXI_DRAM_CTL0_BASE; in mctl_set_pir()182 (struct sunxi_mctl_ctl_reg *)SUNXI_DRAM_CTL0_BASE; in mctl_data_train_cfg()193 (struct sunxi_mctl_ctl_reg *)SUNXI_DRAM_CTL0_BASE; in mctl_train_dram()204 (struct sunxi_mctl_ctl_reg *)SUNXI_DRAM_CTL0_BASE; in mctl_channel_init()299 (struct sunxi_mctl_ctl_reg *)SUNXI_DRAM_CTL0_BASE; in mctl_sys_init()332 (struct sunxi_mctl_ctl_reg *)SUNXI_DRAM_CTL0_BASE; in sunxi_dram_init()
88 (struct sunxi_mctl_ctl_reg *)SUNXI_DRAM_CTL0_BASE; in auto_set_timing_para()205 (struct sunxi_mctl_ctl_reg *)SUNXI_DRAM_CTL0_BASE; in mctl_set_pir()214 (struct sunxi_mctl_ctl_reg *)SUNXI_DRAM_CTL0_BASE; in mctl_data_train_cfg()225 (struct sunxi_mctl_ctl_reg *)SUNXI_DRAM_CTL0_BASE; in mctl_train_dram()260 (struct sunxi_mctl_ctl_reg *)SUNXI_DRAM_CTL0_BASE; in mctl_channel_init()393 (struct sunxi_mctl_ctl_reg *)SUNXI_DRAM_CTL0_BASE; in mctl_sys_init()430 (struct sunxi_mctl_ctl_reg *)SUNXI_DRAM_CTL0_BASE; in sunxi_dram_init()
21 (struct sunxi_mctl_ctl_reg *)SUNXI_DRAM_CTL0_BASE; in mctl_phy_init()30 (struct sunxi_mctl_ctl_reg *)SUNXI_DRAM_CTL0_BASE; in mctl_set_bit_delays()270 (struct sunxi_mctl_ctl_reg *)SUNXI_DRAM_CTL0_BASE; in mctl_h3_zq_calibration_quirk()369 (struct sunxi_mctl_ctl_reg *)SUNXI_DRAM_CTL0_BASE; in mctl_sys_init()424 (struct sunxi_mctl_ctl_reg *)SUNXI_DRAM_CTL0_BASE; in mctl_channel_init()689 (struct sunxi_mctl_ctl_reg *)SUNXI_DRAM_CTL0_BASE; in sunxi_dram_init()
182 (struct sunxi_mctl_ctl_reg *)SUNXI_DRAM_CTL0_BASE; in mctl_set_timing_lpddr3()298 (struct sunxi_mctl_ctl_reg *)SUNXI_DRAM_CTL0_BASE; in mctl_sys_init()340 (struct sunxi_mctl_ctl_reg *)SUNXI_DRAM_CTL0_BASE; in mctl_set_addrmap()421 (struct sunxi_mctl_ctl_reg *)SUNXI_DRAM_CTL0_BASE; in mctl_com_init()529 (struct sunxi_mctl_ctl_reg *)SUNXI_DRAM_CTL0_BASE; in mctl_channel_init()
285 mctl_ctl_sched_init(SUNXI_DRAM_CTL0_BASE); in mctl_sys_init()452 mctl_ctl = (struct sunxi_mctl_ctl_reg *)SUNXI_DRAM_CTL0_BASE; in mctl_channel_init()
97 (struct sunxi_mctl_ctl_reg *)SUNXI_DRAM_CTL0_BASE; in mctl_init()
110 mctl_ctl = (struct sunxi_mctl_ctl_reg *)SUNXI_DRAM_CTL0_BASE; in mctl_channel_init()
8 (struct sunxi_mctl_ctl_reg *)SUNXI_DRAM_CTL0_BASE; in mctl_set_timing_params()