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Searched refs:SSPP_VIG1 (Results 1 – 16 of 16) sorted by relevance

/openbmc/linux/drivers/gpu/drm/msm/disp/mdp5/
H A Dmdp5_cfg.c28 [SSPP_VIG0] = 1, [SSPP_VIG1] = 4, [SSPP_VIG2] = 7,
198 [SSPP_VIG0] = 1, [SSPP_VIG1] = 4, [SSPP_VIG2] = 7,
286 [SSPP_VIG0] = 1, [SSPP_VIG1] = 4,
538 [SSPP_VIG0] = 1, [SSPP_VIG1] = 4,
757 [SSPP_VIG0] = 1, [SSPP_VIG1] = 9,
H A Dmdp5_ctl.c293 case SSPP_VIG1: return MDP5_CTL_LAYER_REG_VIG1(stage); in mdp_ctl_blend_mask()
316 case SSPP_VIG1: return MDP5_CTL_LAYER_EXT_REG_VIG1_BIT3; in mdp_ctl_blend_ext_mask()
444 case SSPP_VIG1: return MDP5_CTL_FLUSH_VIG1; in mdp_ctl_flush_mask_pipe()
H A Dmdp5_kms.c688 SSPP_VIG0, SSPP_VIG1, SSPP_VIG2, SSPP_VIG3, in hwpipe_init() enumerator
H A Dmdp5.xml.h77 SSPP_VIG1 = 2, enumerator
551 case SSPP_VIG1: return (mdp5_cfg->pipe_vig.base[1]); in __offset_PIPE()
/openbmc/linux/drivers/gpu/drm/msm/disp/dpu1/
H A Ddpu_hw_top.c114 status->sspp[SSPP_VIG1] = (value >> 6) & 0x3; in dpu_hw_get_danger_status()
226 status->sspp[SSPP_VIG1] = (value >> 6) & 0x1; in dpu_hw_get_safe_status()
H A Ddpu_hw_mdss.h107 SSPP_VIG1, enumerator
H A Ddpu_hw_ctl.c168 case SSPP_VIG1: in dpu_hw_ctl_update_pending_flush_sspp()
426 [SSPP_VIG1] = { { 0, 3, 2 }, { 3, 4 } },
/openbmc/linux/drivers/gpu/drm/msm/disp/dpu1/catalog/
H A Ddpu_4_0_sdm845.h76 .name = "sspp_1", .id = SSPP_VIG1,
H A Ddpu_3_0_msm8998.h78 .name = "sspp_1", .id = SSPP_VIG1,
H A Ddpu_7_0_sm8350.h84 .name = "sspp_1", .id = SSPP_VIG1,
H A Ddpu_6_0_sm8250.h84 .name = "sspp_1", .id = SSPP_VIG1,
H A Ddpu_5_0_sm8150.h85 .name = "sspp_1", .id = SSPP_VIG1,
H A Ddpu_9_0_sm8550.h86 .name = "sspp_1", .id = SSPP_VIG1,
H A Ddpu_5_1_sc8180x.h84 .name = "sspp_1", .id = SSPP_VIG1,
H A Ddpu_8_1_sm8450.h85 .name = "sspp_1", .id = SSPP_VIG1,
H A Ddpu_8_0_sc8280xp.h84 .name = "sspp_1", .id = SSPP_VIG1,