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Searched refs:SSE (Results 1 – 25 of 33) sorted by relevance

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/openbmc/docs/designs/
H A Dredfish-eventservice.md29 - [Upgrade connection for SSE](https://gerrit.openbmc.org/#/c/openbmc/bmcweb/+/13948/)
64 - SSE: BMC shall respond to GET method on URI specific in "ServerSentEventUri"
69 Also SSE subscription data cannot be persistent across service resets/reboots.
79 of maximum 20 connections (Maximum of 10 SSE connections). BMC shall respond
99 2. Server-Sent Events (SSE): Client opens an SSE connection to the service by
120 CONFIGURATION| |SSE(GET) NETWORK PUSH STYLE | |SSE
302 SSE flow diagram:
317 | | SSE(ON ESTABLISHED CONNECTION) | | |
460 1. Server-Sent Event(SSE): It covers details on what is SSE and how connection
627 subscription types such as 'Push style events' and 'SSE' and more detailed are
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H A Dtelemetry.md159 | | Send report as SSE or push-style event | | |
194 | | Send report as SSE or push-style event | | |
241 | | Send report as SSE or push-style event | | |
267 service. Sending metric report as SSE or push-style events shall be done via the
457 Event Service][6] either as push-style event or SSE.
/openbmc/qemu/hw/timer/
H A Dtrace-events87 sse_counter_control_read(uint64_t offset, uint64_t data, unsigned size) "SSE system counter control…
88 sse_counter_control_write(uint64_t offset, uint64_t data, unsigned size) "SSE system counter contro…
89 sse_counter_status_read(uint64_t offset, uint64_t data, unsigned size) "SSE system counter status f…
90 sse_counter_status_write(uint64_t offset, uint64_t data, unsigned size) "SSE system counter status …
91 sse_counter_reset(void) "SSE system counter: reset"
94 sse_timer_read(uint64_t offset, uint64_t data, unsigned size) "SSE system timer read: offset 0x%" P…
95 sse_timer_write(uint64_t offset, uint64_t data, unsigned size) "SSE system timer write: offset 0x%"…
96 sse_timer_reset(void) "SSE system timer: reset"
/openbmc/linux/arch/x86/kernel/
H A Dverify_cpu.S124 jz .Lverify_cpu_no_longmode # only try to force SSE on AMD
127 btr $15,%eax # enable SSE
/openbmc/bmcweb/redfish-core/include/generated/enums/
H A Devent_destination.hpp34 SSE, enumerator
135 {SubscriptionType::SSE, "SSE"},
/openbmc/qemu/docs/system/arm/
H A Dmusca.rst5 of a system using the SSE-200 Subsystem for Embedded. They are
/openbmc/openbmc/meta-openembedded/meta-oe/recipes-devtools/yasm/
H A Dyasm_git.bb1 SUMMARY = "x86 (SSE) assembler supporting NASM and GAS-syntaxes"
/openbmc/openbmc/poky/meta/conf/machine/include/x86/
H A Dtune-i686.inc12 # Set x86 target arch to i686, so that glibc enables SSE optimised memcpy, etc.
H A Dtune-corei7.inc3 # Intel Nehalem CPU with 64-bit extensions, MMX, SSE, SSE2, SSE3, SSSE3, SSE4.1,
H A Dtune-core2.inc3 # Intel Core2 CPU with 64-bit extensions, MMX, SSE, SSE2, SSE3 and SSSE3
/openbmc/qemu/tests/tcg/i386/
H A DREADME21 This program executes most SSE/AVX instructions and generates a text output,
H A DMakefile.target87 $(PYTHON) $(I386_SRC)/test-mmx.py $(I386_SRC)/x86.csv $@ MMX SSE SSE2 SSE3 SSSE3
/openbmc/openbmc/poky/meta/recipes-gnome/epiphany/
H A Depiphany_47.2.bb42 # ANGLE requires SSE support as of webkit 2.40.x on 32 bit x86
/openbmc/openbmc/poky/meta/recipes-multimedia/gstreamer/
H A Dgstreamer1.0-plugins-common.inc16 # bytecode to SIMD instructions for various architectures (currently SSE, MMX,
/openbmc/qemu/hw/misc/
H A Dtrace-events277 armsse_cpu_pwrctrl_read(uint64_t offset, uint64_t data, unsigned size) "SSE-300 CPU_PWRCTRL read: o…
278 armsse_cpu_pwrctrl_write(uint64_t offset, uint64_t data, unsigned size) "SSE-300 CPU_PWRCTRL write:…
281 armsse_cpuid_read(uint64_t offset, uint64_t data, unsigned size) "SSE-200 CPU_IDENTITY read: offset…
282 armsse_cpuid_write(uint64_t offset, uint64_t data, unsigned size) "SSE-200 CPU_IDENTITY write: offs…
285 armsse_mhu_read(uint64_t offset, uint64_t data, unsigned size) "SSE-200 MHU read: offset 0x%" PRIx6…
286 armsse_mhu_write(uint64_t offset, uint64_t data, unsigned size) "SSE-200 MHU write: offset 0x%" PRI…
/openbmc/linux/arch/x86/crypto/
H A Dcrct10dif-pcl-asm_64.S2 # Implement fast CRC-T10DIF computation with SSE and PCLMULQDQ instructions
H A Dchacha-ssse3-x86_64.S231 # the state matrix in SSE registers four times. As we need some scratch
236 # which allows us to do XOR in SSE registers. 8/16-bit word rotation is
/openbmc/qemu/target/s390x/tcg/
H A Dinsn-format.h.inc55 F2(SSE, BD(1,16,20), BD(2,32,36))
/openbmc/linux/tools/arch/x86/kcpuid/
H A Dcpuid.csv75 1, 0, EDX, 25, sse, SSE
246 0xD, 0, EAX, 1, sse, SSE state
361 0x80000001, 0, ECX, 7, misalignsse, Misaligned SSE Mode
/openbmc/qemu/target/i386/tcg/
H A Ddecode-new.c.inc80 * There is a custom size "xh" used to address half of a SSE/AVX operand.
81 * This points to a 64-bit operand for SSE operations, 128-bit operand
348 [5] = X86_OP_ENTRY0(LFENCE, cpuid(SSE) p_00),
350 [7] = X86_OP_ENTRY0(SFENCE, cpuid(SSE) p_00),
629 /* Should be exception type 2 but they do not have legacy SSE equivalents? */
686 /* Should be exception type 2 or 3 but they do not have legacy SSE equivalents? */
1920 case X86_SIZE_ss: /* SSE/AVX scalar single precision */
1932 case X86_SIZE_sd: /* SSE/AVX scalar double precision */
1956 case X86_SIZE_dq: /* SSE/AVX 128-bit */
1982 case X86_SIZE_ps: /* SSE/AVX packed single precision */
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/openbmc/linux/drivers/scsi/aic7xxx/
H A Daic7xxx_pci.c591 #define SSE 0x40 macro
1942 if (status1 & SSE) { in ahc_pci_intr()
1963 if ((status1 & (DPE|SSE|RMA|RTA|STA|DPR)) == 0) { in ahc_pci_intr()
H A Daic79xx.reg1144 field SSE 0x40
1162 field SSE 0x40
1179 field SSE 0x40
1195 field SSE 0x40
1212 field SSE 0x40
1227 field SSE 0x40
1244 field SSE 0x40
/openbmc/openbmc/poky/meta/recipes-sato/webkit/
H A Dwebkitgtk_2.46.5.bb157 # ANGLE requires SSE support as of webkit 2.40.x on 32 bit x86
/openbmc/openbmc/meta-openembedded/meta-oe/recipes-support/webkitgtk/
H A Dwebkitgtk3_2.44.3.bb174 # ANGLE requires SSE support as of webkit 2.40.x on 32 bit x86
/openbmc/qemu/subprojects/packagefiles/berkeley-softfloat-3/
H A Dmeson.build12 sfspedir = sfdir / '8086-SSE'

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