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Searched refs:SSCR1_SPO (Results 1 – 5 of 5) sorted by relevance

/openbmc/u-boot/arch/arm/include/asm/arch-armada100/
H A Dspi.h46 #define SSCR1_SPO (1 << 3) /* Motorola SPI SSPSCLK polarity macro
/openbmc/linux/drivers/spi/
H A Dspi-pxa2xx.c52 | SSCR1_SPH | SSCR1_SPO | SSCR1_LBM)
58 | SSCR1_SPH | SSCR1_SPO | SSCR1_LBM)
65 | SSCR1_SPH | SSCR1_SPO | SSCR1_LBM)
1305 chip->cr1 &= ~(SSCR1_SPO | SSCR1_SPH); in setup()
1307 ((spi->mode & SPI_CPOL) ? SSCR1_SPO : 0); in setup()
/openbmc/linux/include/linux/
H A Dpxa2xx_ssp.h73 #define SSCR1_SPO BIT(3) /* Motorola SPI SSPSCLK polarity setting */ macro
/openbmc/linux/arch/arm/mach-sa1100/include/mach/
H A DSA-1100.h788 #define SSCR1_SPO 0x00000008 /* Sample clock (SCLK) POlarity */ macro
789 #define SSCR1_SClkIactL (SSCR1_SPO*0) /* Sample Clock Inactive Low */
790 #define SSCR1_SClkIactH (SSCR1_SPO*1) /* Sample Clock Inactive High */
/openbmc/u-boot/include/
H A DSA-1100.h1068 #define SSCR1_SPO 0x00000008 /* Sample clock (SCLK) POlarity */ macro
1069 #define SSCR1_SClkIactL (SSCR1_SPO*0) /* Sample Clock Inactive Low */
1070 #define SSCR1_SClkIactH (SSCR1_SPO*1) /* Sample Clock Inactive High */