Searched refs:SRWD (Results 1 – 2 of 2) sorted by relevance
| /openbmc/qemu/tests/qtest/ |
| H A D | aspeed_smc-test.c | 61 SRWD = 0x80, enumerator
475 writeb(ASPEED_FLASH_BASE, SRWD); in test_status_reg_write_protection()
479 g_assert_cmphex(r & SRWD, ==, SRWD); in test_status_reg_write_protection()
490 g_assert_cmphex(r & SRWD, ==, 0); in test_status_reg_write_protection()
499 writeb(ASPEED_FLASH_BASE, SRWD); in test_status_reg_write_protection()
503 g_assert_cmphex(r & SRWD, ==, SRWD); in test_status_reg_write_protection()
515 g_assert_cmphex(r & SRWD, ==, SRWD); in test_status_reg_write_protection()
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| /openbmc/linux/Documentation/devicetree/bindings/mtd/ |
| H A D | jedec,spi-nor.yaml | 78 The status register write disable (SRWD) bit in status register, combined
80 the SRWD bit is set to 1, and the WP# signal is either driven LOW or hard
85 pull-downs) then status register permanently becomes read-only as the SRWD bit
87 the SRWD bit while writing the status register. WP# signal hard strapped to GND
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