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Searched refs:SRR0 (Results 1 – 13 of 13) sorted by relevance

/openbmc/u-boot/arch/powerpc/cpu/mpc8xx/
H A Dstart.S201 EXCEPTION_PROLOG(SRR0, SRR1)
212 EXCEPTION_PROLOG(SRR0, SRR1)
286 mtspr SRR0,r24
314 mtspr SRR0,r2
/openbmc/u-boot/arch/powerpc/cpu/mpc86xx/
H A Dstart.S86 EXCEPTION_PROLOG(SRR0, SRR1)
97 EXCEPTION_PROLOG(SRR0, SRR1)
349 mtspr SRR0, r4
480 mtspr SRR0, r4
507 mtspr SRR0,r24
535 mtspr SRR0,r2
/openbmc/linux/arch/powerpc/kernel/
H A Dhead_32.h38 stw r11, SRR0(r10)
98 lwz r12, SRR0(r12)
H A Dentry_32.S490 RESTORE_xSRR(SRR0,SRR1);
497 RESTORE_xSRR(SRR0,SRR1);
505 RESTORE_xSRR(SRR0,SRR1);
H A Dhead_book3s_32.S317 stw r11, SRR0(r10)
703 lwz r4, SRR0(r10)
H A Dexceptions-64e.S94 SPECIAL_EXC_STORE(r10,SRR0)
169 SPECIAL_EXC_LOAD(r10,SRR0)
H A Dasm-offsets.c127 OFFSET(SRR0, thread_struct, srr0); in main()
/openbmc/u-boot/include/
H A Dppc_asm.tmpl194 * r21, r22 (SRR0), and r23 (SRR1).
226 EXCEPTION_PROLOG(SRR0, SRR1); \
265 EXCEPTION_PROLOG(SRR0, SRR1); \
/openbmc/u-boot/arch/powerpc/cpu/mpc83xx/
H A Dstart.S114 mtspr SRR0, r4
331 EXCEPTION_PROLOG(SRR0, SRR1)
342 EXCEPTION_PROLOG(SRR0, SRR1)
446 mtspr SRR0,r24
474 mtspr SRR0,r2
/openbmc/u-boot/arch/powerpc/cpu/mpc85xx/
H A Dstart.S1261 EXCEPTION_PROLOG(SRR0, SRR1)
1272 EXCEPTION_PROLOG(SRR0, SRR1)
1339 mtspr SRR0,r2
/openbmc/u-boot/arch/powerpc/include/asm/
H A Dprocessor.h675 #define SRR0 SPRN_SRR0 /* Save and Restore Register 0 */ macro
/openbmc/linux/Documentation/powerpc/
H A Dtransactional_memory.rst260 have SRR0 TM = 0 and TS = 00 (ie. TM off and non transaction) and the
H A Dultravisor.rst991 the UV_ESM ultracall. Further ``SRR0`` is expected to contain the
1001 (**not Ultravisor**), at the address specified in ``SRR0`` with the