| /openbmc/linux/drivers/gpu/drm/amd/display/dc/dce/ |
| H A D | dce_link_encoder.h | 45 SRI(DC_HPD_CONTROL, HPD, id)
52 SRI(DIG_BE_CNTL, DIG, id), \
54 SRI(DP_CONFIG, DP, id), \
55 SRI(DP_DPHY_CNTL, DP, id), \
64 SRI(DP_MSE_SAT0, DP, id), \
65 SRI(DP_MSE_SAT1, DP, id), \
66 SRI(DP_MSE_SAT2, DP, id), \
68 SRI(DP_SEC_CNTL, DP, id), \
71 SRI(DP_SEC_CNTL1, DP, id)
88 SRI(DP_CONFIG, DP, id), \
[all …]
|
| H A D | dce_abm.h | 58 SRI(DC_ABM1_HG_MISC_CTRL, ABM, id), \
62 SRI(BL1_PWM_USER_LEVEL, ABM, id), \
66 SRI(DC_ABM1_ACE_THRES_12, ABM, id), \
90 SRI(DC_ABM1_HG_MISC_CTRL, ABM, id), \
94 SRI(BL1_PWM_USER_LEVEL, ABM, id), \
104 SRI(DC_ABM1_HG_MISC_CTRL, ABM, id), \
108 SRI(BL1_PWM_USER_LEVEL, ABM, id), \
112 SRI(DC_ABM1_ACE_THRES_12, ABM, id), \
120 SRI(DC_ABM1_HG_MISC_CTRL, ABM, id), \
124 SRI(BL1_PWM_USER_LEVEL, ABM, id), \
[all …]
|
| H A D | dce_transform.h | 39 SRI(LB_DATA_FORMAT, LB, id), \
70 SRI(DENORM_CONTROL, DCP, id), \
76 SRI(SCL_MODE, SCL, id), \
78 SRI(SCL_CONTROL, SCL, id), \
86 SRI(VIEWPORT_START, SCL, id), \
87 SRI(VIEWPORT_SIZE, SCL, id), \
93 SRI(LB_MEMORY_CTRL, LB, id), \
94 SRI(SCL_UPDATE, SCL, id), \
113 SRI(DATA_FORMAT, LB, id), \
148 SRI(SCL_CONTROL, SCL, id), \
[all …]
|
| H A D | dce_mem_input.h | 35 SRI(GRPH_ENABLE, DCP, id),\
36 SRI(GRPH_CONTROL, DCP, id),\
37 SRI(GRPH_X_START, DCP, id),\
39 SRI(GRPH_X_END, DCP, id),\
40 SRI(GRPH_Y_END, DCP, id),\
41 SRI(GRPH_PITCH, DCP, id),\
42 SRI(HW_ROTATION, DCP, id),\
45 SRI(GRPH_UPDATE, DCP, id),\
67 SRI(GRPH_X_END, DCP, id),\
68 SRI(GRPH_Y_END, DCP, id),\
[all …]
|
| H A D | dce_opp.h | 44 SRI(FMT_DYNAMIC_EXP_CNTL, FMT, id), \
45 SRI(FMT_BIT_DEPTH_CONTROL, FMT, id), \
46 SRI(FMT_CONTROL, FMT, id), \
50 SRI(FMT_CLAMP_CNTL, FMT, id), \
51 SRI(FMT_CLAMP_COMPONENT_R, FMT, id), \
52 SRI(FMT_CLAMP_COMPONENT_G, FMT, id), \
53 SRI(FMT_CLAMP_COMPONENT_B, FMT, id)
78 SRI(CONTROL, FMT_MEMORY, id)
82 SRI(CONTROL, FMT_MEMORY, id)
88 SRI(FMT_CONTROL, FMT, id), \
[all …]
|
| /openbmc/linux/drivers/gpu/drm/amd/display/dc/dcn30/ |
| H A D | dcn30_dpp.h | 34 SRI(CM_DEALPHA, CM, id),\
35 SRI(CM_MEM_PWR_STATUS, CM, id),\
36 SRI(CM_BIAS_CR_R, CM, id),\
37 SRI(CM_BIAS_Y_G_CB_B, CM, id),\
38 SRI(PRE_DEGAM, CNVC_CFG, id),\
99 SRI(OTG_H_BLANK, DSCL, id), \
100 SRI(OTG_V_BLANK, DSCL, id), \
101 SRI(SCL_MODE, DSCL, id), \
110 SRI(MPC_SIZE, DSCL, id), \
120 SRI(RECOUT_SIZE, DSCL, id), \
[all …]
|
| H A D | dcn30_dio_link_encoder.h | 32 SRI(DIG_BE_CNTL, DIG, id), \
36 SRI(DP_CONFIG, DP, id), \
37 SRI(DP_DPHY_CNTL, DP, id), \
40 SRI(DP_DPHY_SYM0, DP, id), \
41 SRI(DP_DPHY_SYM1, DP, id), \
42 SRI(DP_DPHY_SYM2, DP, id), \
44 SRI(DP_LINK_CNTL, DP, id), \
46 SRI(DP_MSE_SAT0, DP, id), \
47 SRI(DP_MSE_SAT1, DP, id), \
48 SRI(DP_MSE_SAT2, DP, id), \
[all …]
|
| H A D | dcn30_dio_stream_encoder.h | 49 SRI(AFMT_CNTL, DIG, id), \
50 SRI(DIG_FE_CNTL, DIG, id), \
53 SRI(HDMI_GC, DIG, id), \
76 SRI(DP_DB_CNTL, DP, id), \
77 SRI(DP_MSA_MISC, DP, id), \
87 SRI(DP_SEC_CNTL, DP, id), \
88 SRI(DP_SEC_CNTL1, DP, id), \
93 SRI(DP_VID_M, DP, id), \
94 SRI(DP_VID_N, DP, id), \
101 SRI(DP_DSC_CNTL, DP, id), \
[all …]
|
| H A D | dcn30_optc.h | 43 SRI(OTG_H_TOTAL, OTG, inst),\
45 SRI(OTG_H_SYNC_A, OTG, inst),\
48 SRI(OTG_V_TOTAL, OTG, inst),\
50 SRI(OTG_V_SYNC_A, OTG, inst),\
52 SRI(OTG_CONTROL, OTG, inst),\
60 SRI(OTG_TRIGA_CNTL, OTG, inst),\
64 SRI(OTG_STATUS, OTG, inst),\
81 SRI(CONTROL, VTG, inst),\
84 SRI(OTG_CRC_CNTL, OTG, inst),\
85 SRI(OTG_CRC_CNTL2, OTG, inst),\
[all …]
|
| /openbmc/linux/drivers/gpu/drm/amd/display/dc/dcn301/ |
| H A D | dcn301_dio_link_encoder.h | 33 SRI(DIG_BE_CNTL, DIG, id), \
37 SRI(DP_CONFIG, DP, id), \
38 SRI(DP_DPHY_CNTL, DP, id), \
41 SRI(DP_DPHY_SYM0, DP, id), \
42 SRI(DP_DPHY_SYM1, DP, id), \
43 SRI(DP_DPHY_SYM2, DP, id), \
45 SRI(DP_LINK_CNTL, DP, id), \
47 SRI(DP_MSE_SAT0, DP, id), \
48 SRI(DP_MSE_SAT1, DP, id), \
49 SRI(DP_MSE_SAT2, DP, id), \
[all …]
|
| /openbmc/linux/drivers/gpu/drm/amd/display/dc/dcn31/ |
| H A D | dcn31_optc.h | 41 SRI(OTG_H_TOTAL, OTG, inst),\
43 SRI(OTG_H_SYNC_A, OTG, inst),\
46 SRI(OTG_V_TOTAL, OTG, inst),\
48 SRI(OTG_V_SYNC_A, OTG, inst),\
50 SRI(OTG_CONTROL, OTG, inst),\
57 SRI(OTG_TRIGA_CNTL, OTG, inst),\
61 SRI(OTG_STATUS, OTG, inst),\
76 SRI(CONTROL, VTG, inst),\
79 SRI(OTG_CRC_CNTL, OTG, inst),\
100 SRI(OTG_CRC_CNTL2, OTG, inst),\
[all …]
|
| H A D | dcn31_dio_link_encoder.h | 34 SRI(DP_DPHY_INTERNAL_CTRL, DP, id), \
67 SRI(TMDS_CTL_BITS, DIG, id), \
68 SRI(RDPCSTX_PHY_CNTL3, RDPCSTX, id), \
69 SRI(RDPCSTX_PHY_CNTL4, RDPCSTX, id), \
70 SRI(RDPCSTX_PHY_CNTL5, RDPCSTX, id), \
71 SRI(RDPCSTX_PHY_CNTL6, RDPCSTX, id), \
81 SRI(RDPCSTX_CNTL, RDPCSTX, id), \
86 SRI(RDPCS_TX_CR_ADDR, RDPCSTX, id), \
87 SRI(RDPCS_TX_CR_DATA, RDPCSTX, id), \
202 SRI(TMDS_CTL_BITS, DIG, id), \
[all …]
|
| H A D | dcn31_hpo_dp_link_encoder.h | 37 SRI(DP_LINK_ENC_CLOCK_CONTROL, DP_LINK_ENC, id), \
38 SRI(DP_DPHY_SYM32_CONTROL, DP_DPHY_SYM32, id), \
39 SRI(DP_DPHY_SYM32_STATUS, DP_DPHY_SYM32, id), \
40 SRI(DP_DPHY_SYM32_TP_CONFIG, DP_DPHY_SYM32, id), \
46 SRI(DP_DPHY_SYM32_TP_CUSTOM0, DP_DPHY_SYM32, id), \
47 SRI(DP_DPHY_SYM32_TP_CUSTOM1, DP_DPHY_SYM32, id), \
57 SRI(DP_DPHY_SYM32_SAT_VC0, DP_DPHY_SYM32, id), \
58 SRI(DP_DPHY_SYM32_SAT_VC1, DP_DPHY_SYM32, id), \
59 SRI(DP_DPHY_SYM32_SAT_VC2, DP_DPHY_SYM32, id), \
60 SRI(DP_DPHY_SYM32_SAT_VC3, DP_DPHY_SYM32, id), \
[all …]
|
| H A D | dcn31_hpo_dp_stream_encoder.h | 58 SRI(DP_SYM32_ENC_CONTROL, DP_SYM32_ENC, id),\
61 SRI(DP_SYM32_ENC_VID_MSA0, DP_SYM32_ENC, id),\
62 SRI(DP_SYM32_ENC_VID_MSA1, DP_SYM32_ENC, id),\
63 SRI(DP_SYM32_ENC_VID_MSA2, DP_SYM32_ENC, id),\
64 SRI(DP_SYM32_ENC_VID_MSA3, DP_SYM32_ENC, id),\
65 SRI(DP_SYM32_ENC_VID_MSA4, DP_SYM32_ENC, id),\
66 SRI(DP_SYM32_ENC_VID_MSA5, DP_SYM32_ENC, id),\
67 SRI(DP_SYM32_ENC_VID_MSA6, DP_SYM32_ENC, id),\
68 SRI(DP_SYM32_ENC_VID_MSA7, DP_SYM32_ENC, id),\
69 SRI(DP_SYM32_ENC_VID_MSA8, DP_SYM32_ENC, id),\
[all …]
|
| /openbmc/linux/drivers/gpu/drm/amd/display/dc/dcn314/ |
| H A D | dcn314_optc.h | 35 SRI(OTG_VREADY_PARAM, OTG, inst),\
42 SRI(OTG_H_TOTAL, OTG, inst),\
44 SRI(OTG_H_SYNC_A, OTG, inst),\
47 SRI(OTG_V_TOTAL, OTG, inst),\
49 SRI(OTG_V_SYNC_A, OTG, inst),\
51 SRI(OTG_CONTROL, OTG, inst),\
58 SRI(OTG_TRIGA_CNTL, OTG, inst),\
62 SRI(OTG_STATUS, OTG, inst),\
77 SRI(CONTROL, VTG, inst),\
80 SRI(OTG_CRC_CNTL, OTG, inst),\
[all …]
|
| H A D | dcn314_dio_stream_encoder.h | 50 SRI(AFMT_CNTL, DIG, id), \
51 SRI(DIG_FE_CNTL, DIG, id), \
54 SRI(HDMI_GC, DIG, id), \
77 SRI(DP_DB_CNTL, DP, id), \
78 SRI(DP_MSA_MISC, DP, id), \
88 SRI(DP_SEC_CNTL, DP, id), \
89 SRI(DP_SEC_CNTL1, DP, id), \
94 SRI(DP_VID_M, DP, id), \
95 SRI(DP_VID_N, DP, id), \
100 SRI(DP_DSC_CNTL, DP, id), \
[all …]
|
| /openbmc/linux/drivers/gpu/drm/amd/display/dc/dcn20/ |
| H A D | dcn20_dpp.h | 43 SRI(CM_BLNDGAM_CONTROL, CM, id), \
97 SRI(CM_BLNDGAM_LUT_DATA, CM, id), \
98 SRI(CM_3DLUT_MODE, CM, id), \
99 SRI(CM_3DLUT_INDEX, CM, id), \
100 SRI(CM_3DLUT_DATA, CM, id), \
101 SRI(CM_3DLUT_DATA_30BIT, CM, id), \
104 SRI(CM_SHAPER_CONTROL, CM, id), \
151 SRI(CM_SHAPER_LUT_INDEX, CM, id)
160 SRI(CM_ICSC_B_C11_C12, CM, id), \
161 SRI(CM_ICSC_B_C33_C34, CM, id)
[all …]
|
| H A D | dcn20_mmhubbub.h | 35 SRI(MCIF_WB_BUFMGR_STATUS, MCIF_WB, inst),\
36 SRI(MCIF_WB_BUF_PITCH, MCIF_WB, inst),\
37 SRI(MCIF_WB_BUF_1_STATUS, MCIF_WB, inst),\
39 SRI(MCIF_WB_BUF_2_STATUS, MCIF_WB, inst),\
41 SRI(MCIF_WB_BUF_3_STATUS, MCIF_WB, inst),\
43 SRI(MCIF_WB_BUF_4_STATUS, MCIF_WB, inst),\
46 SRI(MCIF_WB_SCLK_CHANGE, MCIF_WB, inst),\
49 SRI(MCIF_WB_BUF_1_ADDR_Y, MCIF_WB, inst),\
51 SRI(MCIF_WB_BUF_1_ADDR_C, MCIF_WB, inst),\
68 SRI(MCIF_WB_WATERMARK, MCIF_WB, inst),\
[all …]
|
| /openbmc/linux/drivers/gpu/drm/amd/display/dc/dcn10/ |
| H A D | dcn10_hubp.h | 35 SRI(DCHUBP_CNTL, HUBP, id),\
36 SRI(HUBPREQ_DEBUG_DB, HUBP, id),\
37 SRI(HUBPREQ_DEBUG, HUBP, id),\
38 SRI(DCSURF_ADDR_CONFIG, HUBP, id),\
78 SRI(HUBPRET_CONTROL, HUBPRET, id),\
83 SRI(BLANK_OFFSET_0, HUBPREQ, id),\
84 SRI(BLANK_OFFSET_1, HUBPREQ, id),\
85 SRI(DST_DIMENSIONS, HUBPREQ, id),\
99 SRI(DCN_TTU_QOS_WM, HUBPREQ, id),\
107 SRI(HUBP_CLK_CNTL, HUBP, id)
[all …]
|
| H A D | dcn10_dwb.h | 38 #define SRI(reg_name, block, id)\ macro
52 SRI(WB_ENABLE, CNV, inst),\
53 SRI(WB_EC_CONFIG, CNV, inst),\
54 SRI(CNV_MODE, CNV, inst),\
55 SRI(WB_SOFT_RESET, CNV, inst),\
57 SRI(MCIF_WB_BUF_PITCH, MCIF_WB, inst),\
59 SRI(MCIF_WB_SCLK_CHANGE, MCIF_WB, inst),\
60 SRI(MCIF_WB_BUF_1_ADDR_Y, MCIF_WB, inst),\
62 SRI(MCIF_WB_BUF_1_ADDR_C, MCIF_WB, inst),\
64 SRI(MCIF_WB_BUF_2_ADDR_Y, MCIF_WB, inst),\
[all …]
|
| H A D | dcn10_ipp.h | 35 SRI(FORMAT_CONTROL, CNVC_CFG, id), \
38 SRI(CURSOR0_COLOR0, CNVC_CUR, id), \
39 SRI(CURSOR0_COLOR1, CNVC_CUR, id)
43 SRI(CURSOR_SETTINS, HUBPREQ, id), \
46 SRI(CURSOR_SIZE, CURSOR, id), \
47 SRI(CURSOR_CONTROL, CURSOR, id), \
48 SRI(CURSOR_POSITION, CURSOR, id), \
49 SRI(CURSOR_HOT_SPOT, CURSOR, id), \
50 SRI(CURSOR_DST_OFFSET, CURSOR, id)
57 SRI(CURSOR_SIZE, CURSOR0_, id), \
[all …]
|
| H A D | dcn10_dpp.h | 56 SRI(OTG_H_BLANK, DSCL, id), \
57 SRI(OTG_V_BLANK, DSCL, id), \
58 SRI(SCL_MODE, DSCL, id), \
61 SRI(DSCL_AUTOCAL, DSCL, id), \
62 SRI(DSCL_CONTROL, DSCL, id), \
68 SRI(MPC_SIZE, DSCL, id), \
79 SRI(RECOUT_START, DSCL, id), \
80 SRI(RECOUT_SIZE, DSCL, id), \
116 SRI(CM_CONTROL, CM, id), \
127 SRI(CM_HDR_MULT_COEF, CM, id)
[all …]
|
| H A D | dcn10_stream_encoder.h | 35 SRI(AFMT_CNTL, DIG, id), \
51 SRI(AFMT_60958_0, DIG, id), \
52 SRI(AFMT_60958_1, DIG, id), \
54 SRI(DIG_FE_CNTL, DIG, id), \
58 SRI(HDMI_GC, DIG, id), \
74 SRI(DP_DB_CNTL, DP, id), \
75 SRI(DP_MSA_MISC, DP, id), \
85 SRI(DP_SEC_CNTL, DP, id), \
86 SRI(DP_SEC_CNTL1, DP, id), \
91 SRI(DP_VID_M, DP, id), \
[all …]
|
| H A D | dcn10_optc.h | 42 SRI(OTG_H_TOTAL, OTG, inst),\
44 SRI(OTG_H_SYNC_A, OTG, inst),\
47 SRI(OTG_V_TOTAL, OTG, inst),\
49 SRI(OTG_V_SYNC_A, OTG, inst),\
52 SRI(OTG_CONTROL, OTG, inst),\
56 SRI(OTG_V_TOTAL_MAX, OTG, inst),\
57 SRI(OTG_V_TOTAL_MID, OTG, inst),\
60 SRI(OTG_TRIGA_CNTL, OTG, inst),\
64 SRI(OTG_STATUS, OTG, inst),\
78 SRI(CONTROL, VTG, inst),\
[all …]
|
| /openbmc/linux/drivers/gpu/drm/amd/display/dc/dcn201/ |
| H A D | dcn201_hubp.h | 37 SRI(PREFETCH_SETTINGS, HUBPREQ, id),\
40 SRI(CURSOR_SETTINGS, HUBPREQ, id), \
43 SRI(CURSOR_SIZE, CURSOR0_, id), \
44 SRI(CURSOR_CONTROL, CURSOR0_, id), \
45 SRI(CURSOR_POSITION, CURSOR0_, id), \
46 SRI(CURSOR_HOT_SPOT, CURSOR0_, id), \
50 SRI(DMDATA_CNTL, CURSOR0_, id), \
51 SRI(DMDATA_SW_CNTL, CURSOR0_, id), \
53 SRI(DMDATA_SW_DATA, CURSOR0_, id), \
54 SRI(DMDATA_STATUS, CURSOR0_, id),\
[all …]
|