1*3f68c01bSZhan Liu /* 2*3f68c01bSZhan Liu * Copyright 2012-17 Advanced Micro Devices, Inc. 3*3f68c01bSZhan Liu * 4*3f68c01bSZhan Liu * Permission is hereby granted, free of charge, to any person obtaining a 5*3f68c01bSZhan Liu * copy of this software and associated documentation files (the "Software"), 6*3f68c01bSZhan Liu * to deal in the Software without restriction, including without limitation 7*3f68c01bSZhan Liu * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8*3f68c01bSZhan Liu * and/or sell copies of the Software, and to permit persons to whom the 9*3f68c01bSZhan Liu * Software is furnished to do so, subject to the following conditions: 10*3f68c01bSZhan Liu * 11*3f68c01bSZhan Liu * The above copyright notice and this permission notice shall be included in 12*3f68c01bSZhan Liu * all copies or substantial portions of the Software. 13*3f68c01bSZhan Liu * 14*3f68c01bSZhan Liu * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15*3f68c01bSZhan Liu * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16*3f68c01bSZhan Liu * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17*3f68c01bSZhan Liu * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18*3f68c01bSZhan Liu * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19*3f68c01bSZhan Liu * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20*3f68c01bSZhan Liu * OTHER DEALINGS IN THE SOFTWARE. 21*3f68c01bSZhan Liu * 22*3f68c01bSZhan Liu * Authors: AMD 23*3f68c01bSZhan Liu * 24*3f68c01bSZhan Liu */ 25*3f68c01bSZhan Liu 26*3f68c01bSZhan Liu #ifndef __DC_MEM_INPUT_DCN201_H__ 27*3f68c01bSZhan Liu #define __DC_MEM_INPUT_DCN201_H__ 28*3f68c01bSZhan Liu 29*3f68c01bSZhan Liu #include "../dcn10/dcn10_hubp.h" 30*3f68c01bSZhan Liu #include "../dcn20/dcn20_hubp.h" 31*3f68c01bSZhan Liu 32*3f68c01bSZhan Liu #define TO_DCN201_HUBP(hubp)\ 33*3f68c01bSZhan Liu container_of(hubp, struct dcn201_hubp, base) 34*3f68c01bSZhan Liu 35*3f68c01bSZhan Liu #define HUBP_REG_LIST_DCN201(id)\ 36*3f68c01bSZhan Liu HUBP_REG_LIST_DCN(id),\ 37*3f68c01bSZhan Liu SRI(PREFETCH_SETTINGS, HUBPREQ, id),\ 38*3f68c01bSZhan Liu SRI(PREFETCH_SETTINGS_C, HUBPREQ, id),\ 39*3f68c01bSZhan Liu SRI(DCSURF_FLIP_CONTROL2, HUBPREQ, id), \ 40*3f68c01bSZhan Liu SRI(CURSOR_SETTINGS, HUBPREQ, id), \ 41*3f68c01bSZhan Liu SRI(CURSOR_SURFACE_ADDRESS_HIGH, CURSOR0_, id), \ 42*3f68c01bSZhan Liu SRI(CURSOR_SURFACE_ADDRESS, CURSOR0_, id), \ 43*3f68c01bSZhan Liu SRI(CURSOR_SIZE, CURSOR0_, id), \ 44*3f68c01bSZhan Liu SRI(CURSOR_CONTROL, CURSOR0_, id), \ 45*3f68c01bSZhan Liu SRI(CURSOR_POSITION, CURSOR0_, id), \ 46*3f68c01bSZhan Liu SRI(CURSOR_HOT_SPOT, CURSOR0_, id), \ 47*3f68c01bSZhan Liu SRI(CURSOR_DST_OFFSET, CURSOR0_, id), \ 48*3f68c01bSZhan Liu SRI(DMDATA_ADDRESS_HIGH, CURSOR0_, id), \ 49*3f68c01bSZhan Liu SRI(DMDATA_ADDRESS_LOW, CURSOR0_, id), \ 50*3f68c01bSZhan Liu SRI(DMDATA_CNTL, CURSOR0_, id), \ 51*3f68c01bSZhan Liu SRI(DMDATA_SW_CNTL, CURSOR0_, id), \ 52*3f68c01bSZhan Liu SRI(DMDATA_QOS_CNTL, CURSOR0_, id), \ 53*3f68c01bSZhan Liu SRI(DMDATA_SW_DATA, CURSOR0_, id), \ 54*3f68c01bSZhan Liu SRI(DMDATA_STATUS, CURSOR0_, id),\ 55*3f68c01bSZhan Liu SRI(FLIP_PARAMETERS_0, HUBPREQ, id),\ 56*3f68c01bSZhan Liu SRI(FLIP_PARAMETERS_2, HUBPREQ, id) 57*3f68c01bSZhan Liu 58*3f68c01bSZhan Liu #define HUBP_MASK_SH_LIST_DCN201(mask_sh)\ 59*3f68c01bSZhan Liu HUBP_MASK_SH_LIST_DCN(mask_sh),\ 60*3f68c01bSZhan Liu HUBP_SF(HUBPREQ0_PREFETCH_SETTINGS, DST_Y_PREFETCH, mask_sh),\ 61*3f68c01bSZhan Liu HUBP_SF(HUBPREQ0_PREFETCH_SETTINGS, VRATIO_PREFETCH, mask_sh),\ 62*3f68c01bSZhan Liu HUBP_SF(HUBPREQ0_PREFETCH_SETTINGS_C, VRATIO_PREFETCH_C, mask_sh),\ 63*3f68c01bSZhan Liu HUBP_SF(HUBPREQ0_DCSURF_FLIP_CONTROL2, SURFACE_TRIPLE_BUFFER_ENABLE, mask_sh),\ 64*3f68c01bSZhan Liu HUBP_SF(HUBPREQ0_CURSOR_SETTINGS, CURSOR0_DST_Y_OFFSET, mask_sh), \ 65*3f68c01bSZhan Liu HUBP_SF(HUBPREQ0_CURSOR_SETTINGS, CURSOR0_CHUNK_HDL_ADJUST, mask_sh), \ 66*3f68c01bSZhan Liu HUBP_SF(CURSOR0_0_CURSOR_SURFACE_ADDRESS_HIGH, CURSOR_SURFACE_ADDRESS_HIGH, mask_sh), \ 67*3f68c01bSZhan Liu HUBP_SF(CURSOR0_0_CURSOR_SURFACE_ADDRESS, CURSOR_SURFACE_ADDRESS, mask_sh), \ 68*3f68c01bSZhan Liu HUBP_SF(CURSOR0_0_CURSOR_SIZE, CURSOR_WIDTH, mask_sh), \ 69*3f68c01bSZhan Liu HUBP_SF(CURSOR0_0_CURSOR_SIZE, CURSOR_HEIGHT, mask_sh), \ 70*3f68c01bSZhan Liu HUBP_SF(CURSOR0_0_CURSOR_CONTROL, CURSOR_MODE, mask_sh), \ 71*3f68c01bSZhan Liu HUBP_SF(CURSOR0_0_CURSOR_CONTROL, CURSOR_2X_MAGNIFY, mask_sh), \ 72*3f68c01bSZhan Liu HUBP_SF(CURSOR0_0_CURSOR_CONTROL, CURSOR_PITCH, mask_sh), \ 73*3f68c01bSZhan Liu HUBP_SF(CURSOR0_0_CURSOR_CONTROL, CURSOR_LINES_PER_CHUNK, mask_sh), \ 74*3f68c01bSZhan Liu HUBP_SF(CURSOR0_0_CURSOR_CONTROL, CURSOR_ENABLE, mask_sh), \ 75*3f68c01bSZhan Liu HUBP_SF(CURSOR0_0_CURSOR_POSITION, CURSOR_X_POSITION, mask_sh), \ 76*3f68c01bSZhan Liu HUBP_SF(CURSOR0_0_CURSOR_POSITION, CURSOR_Y_POSITION, mask_sh), \ 77*3f68c01bSZhan Liu HUBP_SF(CURSOR0_0_CURSOR_HOT_SPOT, CURSOR_HOT_SPOT_X, mask_sh), \ 78*3f68c01bSZhan Liu HUBP_SF(CURSOR0_0_CURSOR_HOT_SPOT, CURSOR_HOT_SPOT_Y, mask_sh), \ 79*3f68c01bSZhan Liu HUBP_SF(CURSOR0_0_CURSOR_DST_OFFSET, CURSOR_DST_X_OFFSET, mask_sh), \ 80*3f68c01bSZhan Liu HUBP_SF(CURSOR0_0_DMDATA_ADDRESS_HIGH, DMDATA_ADDRESS_HIGH, mask_sh), \ 81*3f68c01bSZhan Liu HUBP_SF(CURSOR0_0_DMDATA_CNTL, DMDATA_MODE, mask_sh), \ 82*3f68c01bSZhan Liu HUBP_SF(CURSOR0_0_DMDATA_CNTL, DMDATA_UPDATED, mask_sh), \ 83*3f68c01bSZhan Liu HUBP_SF(CURSOR0_0_DMDATA_CNTL, DMDATA_REPEAT, mask_sh), \ 84*3f68c01bSZhan Liu HUBP_SF(CURSOR0_0_DMDATA_CNTL, DMDATA_SIZE, mask_sh), \ 85*3f68c01bSZhan Liu HUBP_SF(CURSOR0_0_DMDATA_SW_CNTL, DMDATA_SW_UPDATED, mask_sh), \ 86*3f68c01bSZhan Liu HUBP_SF(CURSOR0_0_DMDATA_SW_CNTL, DMDATA_SW_REPEAT, mask_sh), \ 87*3f68c01bSZhan Liu HUBP_SF(CURSOR0_0_DMDATA_SW_CNTL, DMDATA_SW_SIZE, mask_sh), \ 88*3f68c01bSZhan Liu HUBP_SF(CURSOR0_0_DMDATA_QOS_CNTL, DMDATA_QOS_MODE, mask_sh), \ 89*3f68c01bSZhan Liu HUBP_SF(CURSOR0_0_DMDATA_QOS_CNTL, DMDATA_QOS_LEVEL, mask_sh), \ 90*3f68c01bSZhan Liu HUBP_SF(CURSOR0_0_DMDATA_QOS_CNTL, DMDATA_DL_DELTA, mask_sh),\ 91*3f68c01bSZhan Liu HUBP_SF(HUBPREQ0_FLIP_PARAMETERS_0, DST_Y_PER_VM_FLIP, mask_sh),\ 92*3f68c01bSZhan Liu HUBP_SF(HUBPREQ0_FLIP_PARAMETERS_0, DST_Y_PER_ROW_FLIP, mask_sh),\ 93*3f68c01bSZhan Liu HUBP_SF(HUBPREQ0_FLIP_PARAMETERS_2, REFCYC_PER_META_CHUNK_FLIP_L, mask_sh),\ 94*3f68c01bSZhan Liu HUBP_SF(HUBP0_DCHUBP_CNTL, HUBP_VREADY_AT_OR_AFTER_VSYNC, mask_sh),\ 95*3f68c01bSZhan Liu HUBP_SF(HUBP0_DCHUBP_CNTL, HUBP_DISABLE_STOP_DATA_DURING_VM, mask_sh),\ 96*3f68c01bSZhan Liu HUBP_SF(HUBPREQ0_DCSURF_FLIP_CONTROL, HUBPREQ_MASTER_UPDATE_LOCK_STATUS, mask_sh) 97*3f68c01bSZhan Liu 98*3f68c01bSZhan Liu #define DCN201_HUBP_REG_VARIABLE_LIST \ 99*3f68c01bSZhan Liu DCN2_HUBP_REG_COMMON_VARIABLE_LIST 100*3f68c01bSZhan Liu 101*3f68c01bSZhan Liu #define DCN201_HUBP_REG_FIELD_VARIABLE_LIST(type) \ 102*3f68c01bSZhan Liu DCN2_HUBP_REG_FIELD_VARIABLE_LIST(type) 103*3f68c01bSZhan Liu 104*3f68c01bSZhan Liu struct dcn201_hubp_registers { 105*3f68c01bSZhan Liu DCN201_HUBP_REG_VARIABLE_LIST; 106*3f68c01bSZhan Liu }; 107*3f68c01bSZhan Liu 108*3f68c01bSZhan Liu struct dcn201_hubp_shift { 109*3f68c01bSZhan Liu DCN201_HUBP_REG_FIELD_VARIABLE_LIST(uint8_t); 110*3f68c01bSZhan Liu }; 111*3f68c01bSZhan Liu 112*3f68c01bSZhan Liu struct dcn201_hubp_mask { 113*3f68c01bSZhan Liu DCN201_HUBP_REG_FIELD_VARIABLE_LIST(uint32_t); 114*3f68c01bSZhan Liu }; 115*3f68c01bSZhan Liu 116*3f68c01bSZhan Liu struct dcn201_hubp { 117*3f68c01bSZhan Liu struct hubp base; 118*3f68c01bSZhan Liu struct dcn_hubp_state state; 119*3f68c01bSZhan Liu const struct dcn201_hubp_registers *hubp_regs; 120*3f68c01bSZhan Liu const struct dcn201_hubp_shift *hubp_shift; 121*3f68c01bSZhan Liu const struct dcn201_hubp_mask *hubp_mask; 122*3f68c01bSZhan Liu }; 123*3f68c01bSZhan Liu 124*3f68c01bSZhan Liu bool dcn201_hubp_construct( 125*3f68c01bSZhan Liu struct dcn201_hubp *hubp201, 126*3f68c01bSZhan Liu struct dc_context *ctx, 127*3f68c01bSZhan Liu uint32_t inst, 128*3f68c01bSZhan Liu const struct dcn201_hubp_registers *hubp_regs, 129*3f68c01bSZhan Liu const struct dcn201_hubp_shift *hubp_shift, 130*3f68c01bSZhan Liu const struct dcn201_hubp_mask *hubp_mask); 131*3f68c01bSZhan Liu 132*3f68c01bSZhan Liu #endif /* __DC_HWSS_DCN20_H__ */ 133