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Searched refs:SRC2 (Results 1 – 4 of 4) sorted by relevance

/openbmc/qemu/tests/tcg/hexagon/
H A Dusr.c462 FUNC, SRC1, SRC2, RES, USR_RES) \ argument
466 SRC2TYPE src2 = SRC2; \
473 #define TEST_P_OP_PP(FUNC, SRC1, SRC2, RES, USR_RES) \ argument
475 FUNC, SRC1, SRC2, RES, USR_RES)
477 #define TEST_R_OP_PP(FUNC, SRC1, SRC2, RES, USR_RES) \ argument
479 FUNC, SRC1, SRC2, RES, USR_RES)
481 #define TEST_P_OP_RR(FUNC, SRC1, SRC2, RES, USR_RES) \ argument
483 FUNC, SRC1, SRC2, RES, USR_RES)
485 #define TEST_R_OP_RR(FUNC, SRC1, SRC2, RES, USR_RES) \ argument
487 FUNC, SRC1, SRC2, RES, USR_RES)
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/openbmc/u-boot/arch/arm/mach-tegra/tegra124/
H A Dclock.c144 CLK(PERIPH), CLK(NONE), CLK(OSC), CLK(SRC2),
/openbmc/u-boot/arch/arm/mach-tegra/tegra210/
H A Dclock.c146 CLK(PERIPH), CLK(NONE), CLK(OSC), CLK(SRC2),
/openbmc/qemu/target/hexagon/imported/mmvec/
H A Dext.idef1204 #define MMVEC_ADDSAT_MIX(TAGEND,SATF,WIDTH,DEST,SRC1,SRC2)\
1205 …d32."#DEST"=vadd(Vu32."#SRC1",Vv32."#SRC2"):sat", "Vector Add mixed", VdV.DEST[i] = SATF(VuV.S…
1206 …d32."#DEST"=vsub(Vu32."#SRC1",Vv32."#SRC2"):sat", "Vector Sub mixed", VdV.DEST[i] = SATF(VuV.S…