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/openbmc/linux/Documentation/arch/arm/stm32/
H A Dstm32-dma-mdma-chaining.rst29 the system SRAM) for different peripheral. It can access external RAMs but
113 bad with DDR, while they are optimal with SRAM. Hence the SRAM buffer used
124 | DMA_SxM0AR |<=>| | SRAM | |<=>| []-[]...[] |
140 **1. Allocate a SRAM buffer**
143 your board device tree to define your SRAM pool.
155 SRAM.
169 Then get this SRAM pool in your foo driver and allocate your SRAM buffer.
320 config.dst_addr = sram_dma_buf; // SRAM buffer
327 mdma_conf.src_addr = sram_dma_buf; // SRAM buffer
340 dmaengine_prep_dma_cyclic()) with the new SRAM buffer.
[all …]
/openbmc/linux/Documentation/devicetree/bindings/crypto/
H A Dmv_cesa.txt9 region. Can also contain an entry for the SRAM attached to the CESA,
17 - marvell,crypto-srams: phandle to crypto SRAM definitions
20 - marvell,crypto-sram-size: SRAM size reserved for crypto operations, if not
21 specified the whole SRAM is used (2KB)
H A Dmarvell-cesa.txt13 region. Can also contain an entry for the SRAM attached to the CESA,
26 - marvell,crypto-srams: phandle to crypto SRAM definitions
29 - marvell,crypto-sram-size: SRAM size reserved for crypto operations, if not
30 specified the whole SRAM is used (2KB)
/openbmc/linux/arch/arm/boot/dts/nxp/lpc/
H A Dlpc4357.dtsi26 reg = <0x10000000 0x8000>; /* 32 KiB local SRAM */
31 reg = <0x10080000 0xa000>; /* 32 + 8 KiB local SRAM */
36 reg = <0x20000000 0x10000>; /* 4 x 16 KiB AHB SRAM */
H A Dlpc4350.dtsi26 reg = <0x10000000 0x20000>; /* 96 + 32 KiB local SRAM */
31 reg = <0x10080000 0x12000>; /* 64 + 8 KiB local SRAM */
36 reg = <0x20000000 0x10000>; /* 4 x 16 KiB AHB SRAM */
/openbmc/linux/Documentation/devicetree/bindings/memory-controllers/
H A Dcanaan,k210-sram.yaml7 title: Canaan K210 SRAM memory controller
10 The Canaan K210 SRAM memory controller is responsible for the system's 8 MiB
11 of SRAM. The controller is initialised by the bootloader, which configures
H A Dti,gpmc.yaml16 - Asynchronous SRAM-like memories and ASICs
19 - Pseudo-SRAM devices
85 - description: NOR/SRAM bank 0
86 - description: NOR/SRAM bank 1
130 bus. The device can be a NAND chip, SRAM device, NOR device
H A Darm,pl35x-smc.yaml15 SRAM or NOR) depending on the specific configuration.
79 mapped controllers such as NOR and SRAM controllers.
145 0x1 0x0 0xe2000000 0x2000000 /* SRAM/NOR CS0 region */
146 0x2 0x0 0xe4000000 0x2000000>; /* SRAM/NOR CS1 region */
/openbmc/linux/Documentation/devicetree/bindings/sram/
H A Dsram.yaml7 title: Generic on-chip SRAM
47 SRAM clock.
62 The flag indicating, that SRAM memory region has not to be remapped
101 IO mem address range, relative to the SRAM range.
106 Indicates that the particular reserved SRAM area is addressable
112 Indicates that the reserved SRAM area may be accessed outside
159 reg = <0x5c000000 0x40000>; /* 256 KiB SRAM at address 0x5c000000 */
271 // check if this SRAM is usable first.
273 // 256 KiB secure SRAM at 0x20000
H A Dallwinner,sun4i-a10-system-control.yaml14 The SRAM controller found on most Allwinner devices is represented
15 by a regular node for the SRAM controller itself, with sub-nodes
16 representing the SRAM handled by the SRAM controller.
/openbmc/qemu/docs/system/arm/
H A Dstellaris.rst9 - 64k Flash and 8k SRAM.
21 - 256k Flash and 64k SRAM.
/openbmc/linux/Documentation/devicetree/bindings/net/
H A Dmarvell-orion-net.txt43 - marvell,tx-sram-addr: address of transmit descriptor buffer located in SRAM.
44 - marvell,tx-sram-size: size of transmit descriptor buffer located in SRAM.
46 - marvell,rx-sram-addr: address of receive descriptor buffer located in SRAM.
47 - marvell,rx-sram-size: size of receive descriptor buffer located in SRAM.
H A Dallwinner,sun4i-a10-emac.yaml30 description: Phandle to the device SRAM
34 - description: phandle to SRAM
H A Dmarvell-neta-bm.txt8 - internal-mem: a phandle to BM internal SRAM definition.
38 - internal SRAM node:
/openbmc/linux/drivers/soc/sunxi/
H A DKconfig19 Say y here to enable the SRAM controller support. This
20 device is responsible on mapping the SRAM in the sunXi SoCs
/openbmc/linux/arch/arm/mach-at91/
H A DKconfig91 select SRAM if PM
108 select SRAM if PM
140 select SRAM if PM
216 select SRAM if PM
236 select SRAM if PM
/openbmc/u-boot/doc/SPL/
H A DREADME.omap326 starts at the top of SRAM (which is configurable) and grows downward. The
27 space between the top of SRAM and the enforced upper bound on the size of the
32 SRAM: 0x40200000 - 0x4020FFFF
/openbmc/linux/Documentation/devicetree/bindings/rtc/
H A Dtrivial-rtc.yaml31 # Extremely Accurate I²C RTC with Integrated Crystal and SRAM
44 # Intersil ISL1208 Low Power RTC with Battery Backed SRAM
46 # Intersil ISL1218 Low Power RTC with Battery Backed SRAM
/openbmc/linux/drivers/memory/
H A DKconfig11 for DRAM (SDR, DDR), ROM, SRAM and others. The drivers features
112 memory drives like NOR, NAND, OneNAND, SRAM.
129 tristate "Texas Instruments EMIF SRAM driver"
131 depends on SRAM
135 the EMIF PM code must run from on-chip SRAM late in the suspend
157 devices such as NOR, NAND, SRAM, and FPGA.
181 memory devices such as NAND and SRAM.
225 devices (like SRAM, ethernet adapters, FPGAs, LCD displays, ...) on
/openbmc/linux/Documentation/devicetree/bindings/mtd/
H A Darm,pl353-nand-r2p1.yaml41 0x1 0x0 0xe2000000 0x2000000 /* SRAM/NOR CS0 region */
42 0x2 0x0 0xe4000000 0x2000000>; /* SRAM/NOR CS1 region */
/openbmc/linux/Documentation/devicetree/bindings/bus/
H A Dallwinner,sun50i-a64-de2.yaml35 The SRAM that needs to be claimed to access the display engine
40 - description: phandle to SRAM
/openbmc/bmcweb/redfish-core/include/generated/enums/
H A Dprocessor.hpp49 SRAM, enumerator
135 {ProcessorMemoryType::SRAM, "SRAM"},
/openbmc/linux/arch/m68k/q40/
H A DREADME52 Upon startup the kernel will usually output "ABCQGHIJ" into the SRAM,
55 **Changed** to preserve SRAM contents by default, this is only done when
56 requested - SRAM must start with '%LX$' signature to do this. '-d' option
59 SRAM can also be used as additional console device, use debug=mem.
60 This will save kernel startup msgs into SRAM, the screen will display
/openbmc/u-boot/board/work-microwave/work_92105/
H A DREADME24 1. spl/u-boot-spl.bin SPL, intended to run from SRAM at address 0.
25 This file can be loaded in SRAM through a JTAG
50 code to load SPL into SRAM and branch into it.
/openbmc/linux/Documentation/devicetree/bindings/media/
H A Dallwinner,sun4i-a10-video-engine.yaml53 - description: phandle to SRAM
55 description: Phandle to the device SRAM

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