Searched refs:SPRN_DCCR (Results 1 – 3 of 3) sorted by relevance
80 mtspr(SPRN_DCCR, 0xFFFF0000); /* 2GByte of data space at 0x0. */ in MMU_init_hw()
180 #define SPRN_DCCR 0x3FA /* Data Cache Cacheability Register */ macro
173 #define SPRN_DCCR 0x3FA /* Data Cache Cacheability Register */ macro