12874c5fdSThomas Gleixner // SPDX-License-Identifier: GPL-2.0-or-later
227e23b5fSChristophe Leroy /*
327e23b5fSChristophe Leroy * This file contains the routines for initializing the MMU
427e23b5fSChristophe Leroy * on the 4xx series of chips.
527e23b5fSChristophe Leroy * -- paulus
627e23b5fSChristophe Leroy *
727e23b5fSChristophe Leroy * Derived from arch/ppc/mm/init.c:
827e23b5fSChristophe Leroy * Copyright (C) 1995-1996 Gary Thomas (gdt@linuxppc.org)
927e23b5fSChristophe Leroy *
1027e23b5fSChristophe Leroy * Modifications by Paul Mackerras (PowerMac) (paulus@cs.anu.edu.au)
1127e23b5fSChristophe Leroy * and Cort Dougan (PReP) (cort@cs.nmt.edu)
1227e23b5fSChristophe Leroy * Copyright (C) 1996 Paul Mackerras
1327e23b5fSChristophe Leroy *
1427e23b5fSChristophe Leroy * Derived from "arch/i386/mm/init.c"
1527e23b5fSChristophe Leroy * Copyright (C) 1991, 1992, 1993, 1994 Linus Torvalds
1627e23b5fSChristophe Leroy */
1727e23b5fSChristophe Leroy
1827e23b5fSChristophe Leroy #include <linux/signal.h>
1927e23b5fSChristophe Leroy #include <linux/sched.h>
2027e23b5fSChristophe Leroy #include <linux/kernel.h>
2127e23b5fSChristophe Leroy #include <linux/errno.h>
2227e23b5fSChristophe Leroy #include <linux/string.h>
2327e23b5fSChristophe Leroy #include <linux/types.h>
2427e23b5fSChristophe Leroy #include <linux/ptrace.h>
2527e23b5fSChristophe Leroy #include <linux/mman.h>
2627e23b5fSChristophe Leroy #include <linux/mm.h>
2727e23b5fSChristophe Leroy #include <linux/swap.h>
2827e23b5fSChristophe Leroy #include <linux/stddef.h>
2927e23b5fSChristophe Leroy #include <linux/vmalloc.h>
3027e23b5fSChristophe Leroy #include <linux/init.h>
3127e23b5fSChristophe Leroy #include <linux/delay.h>
3227e23b5fSChristophe Leroy #include <linux/highmem.h>
3327e23b5fSChristophe Leroy #include <linux/memblock.h>
3427e23b5fSChristophe Leroy
3527e23b5fSChristophe Leroy #include <asm/io.h>
3627e23b5fSChristophe Leroy #include <asm/mmu_context.h>
3727e23b5fSChristophe Leroy #include <asm/mmu.h>
3827e23b5fSChristophe Leroy #include <linux/uaccess.h>
3927e23b5fSChristophe Leroy #include <asm/smp.h>
4027e23b5fSChristophe Leroy #include <asm/bootx.h>
4127e23b5fSChristophe Leroy #include <asm/machdep.h>
4227e23b5fSChristophe Leroy #include <asm/setup.h>
4327e23b5fSChristophe Leroy
4427e23b5fSChristophe Leroy #include <mm/mmu_decl.h>
4527e23b5fSChristophe Leroy
4627e23b5fSChristophe Leroy /*
4727e23b5fSChristophe Leroy * MMU_init_hw does the chip-specific initialization of the MMU hardware.
4827e23b5fSChristophe Leroy */
MMU_init_hw(void)4927e23b5fSChristophe Leroy void __init MMU_init_hw(void)
5027e23b5fSChristophe Leroy {
5127e23b5fSChristophe Leroy /*
5227e23b5fSChristophe Leroy * The Zone Protection Register (ZPR) defines how protection will
5327e23b5fSChristophe Leroy * be applied to every page which is a member of a given zone. At
5427e23b5fSChristophe Leroy * present, we utilize only two of the 4xx's zones.
5527e23b5fSChristophe Leroy * The zone index bits (of ZSEL) in the PTE are used for software
5627e23b5fSChristophe Leroy * indicators, except the LSB. For user access, zone 1 is used,
5727e23b5fSChristophe Leroy * for kernel access, zone 0 is used. We set all but zone 1
5827e23b5fSChristophe Leroy * to zero, allowing only kernel access as indicated in the PTE.
5927e23b5fSChristophe Leroy * For zone 1, we set a 01 binary (a value of 10 will not work)
6027e23b5fSChristophe Leroy * to allow user access as indicated in the PTE. This also allows
6127e23b5fSChristophe Leroy * kernel access as indicated in the PTE.
6227e23b5fSChristophe Leroy */
6327e23b5fSChristophe Leroy
6427e23b5fSChristophe Leroy mtspr(SPRN_ZPR, 0x10000000);
6527e23b5fSChristophe Leroy
6627e23b5fSChristophe Leroy flush_instruction_cache();
6727e23b5fSChristophe Leroy
6827e23b5fSChristophe Leroy /*
6927e23b5fSChristophe Leroy * Set up the real-mode cache parameters for the exception vector
7027e23b5fSChristophe Leroy * handlers (which are run in real-mode).
7127e23b5fSChristophe Leroy */
7227e23b5fSChristophe Leroy
7327e23b5fSChristophe Leroy mtspr(SPRN_DCWR, 0x00000000); /* All caching is write-back */
7427e23b5fSChristophe Leroy
7527e23b5fSChristophe Leroy /*
7627e23b5fSChristophe Leroy * Cache instruction and data space where the exception
7727e23b5fSChristophe Leroy * vectors and the kernel live in real-mode.
7827e23b5fSChristophe Leroy */
7927e23b5fSChristophe Leroy
8027e23b5fSChristophe Leroy mtspr(SPRN_DCCR, 0xFFFF0000); /* 2GByte of data space at 0x0. */
8127e23b5fSChristophe Leroy mtspr(SPRN_ICCR, 0xFFFF0000); /* 2GByte of instr. space at 0x0. */
8227e23b5fSChristophe Leroy }
8327e23b5fSChristophe Leroy
8427e23b5fSChristophe Leroy #define LARGE_PAGE_SIZE_16M (1<<24)
8527e23b5fSChristophe Leroy #define LARGE_PAGE_SIZE_4M (1<<22)
8627e23b5fSChristophe Leroy
mmu_mapin_ram(unsigned long base,unsigned long top)8727e23b5fSChristophe Leroy unsigned long __init mmu_mapin_ram(unsigned long base, unsigned long top)
8827e23b5fSChristophe Leroy {
8927e23b5fSChristophe Leroy unsigned long v, s, mapped;
9027e23b5fSChristophe Leroy phys_addr_t p;
9127e23b5fSChristophe Leroy
9227e23b5fSChristophe Leroy v = KERNELBASE;
9327e23b5fSChristophe Leroy p = 0;
9427e23b5fSChristophe Leroy s = total_lowmem;
9527e23b5fSChristophe Leroy
96*513f5bbaSChristophe Leroy if (IS_ENABLED(CONFIG_KFENCE))
97*513f5bbaSChristophe Leroy return 0;
98*513f5bbaSChristophe Leroy
99*513f5bbaSChristophe Leroy if (debug_pagealloc_enabled())
100*513f5bbaSChristophe Leroy return 0;
101*513f5bbaSChristophe Leroy
102*513f5bbaSChristophe Leroy if (strict_kernel_rwx_enabled())
10327e23b5fSChristophe Leroy return 0;
10427e23b5fSChristophe Leroy
10527e23b5fSChristophe Leroy while (s >= LARGE_PAGE_SIZE_16M) {
10627e23b5fSChristophe Leroy pmd_t *pmdp;
1072c74e258SChristophe Leroy unsigned long val = p | _PMD_SIZE_16M | _PAGE_EXEC | _PAGE_RW;
10827e23b5fSChristophe Leroy
109e05c7b1fSMike Rapoport pmdp = pmd_off_k(v);
11027e23b5fSChristophe Leroy *pmdp++ = __pmd(val);
11127e23b5fSChristophe Leroy *pmdp++ = __pmd(val);
11227e23b5fSChristophe Leroy *pmdp++ = __pmd(val);
11327e23b5fSChristophe Leroy *pmdp++ = __pmd(val);
11427e23b5fSChristophe Leroy
11527e23b5fSChristophe Leroy v += LARGE_PAGE_SIZE_16M;
11627e23b5fSChristophe Leroy p += LARGE_PAGE_SIZE_16M;
11727e23b5fSChristophe Leroy s -= LARGE_PAGE_SIZE_16M;
11827e23b5fSChristophe Leroy }
11927e23b5fSChristophe Leroy
12027e23b5fSChristophe Leroy while (s >= LARGE_PAGE_SIZE_4M) {
12127e23b5fSChristophe Leroy pmd_t *pmdp;
1222c74e258SChristophe Leroy unsigned long val = p | _PMD_SIZE_4M | _PAGE_EXEC | _PAGE_RW;
12327e23b5fSChristophe Leroy
124e05c7b1fSMike Rapoport pmdp = pmd_off_k(v);
12527e23b5fSChristophe Leroy *pmdp = __pmd(val);
12627e23b5fSChristophe Leroy
12727e23b5fSChristophe Leroy v += LARGE_PAGE_SIZE_4M;
12827e23b5fSChristophe Leroy p += LARGE_PAGE_SIZE_4M;
12927e23b5fSChristophe Leroy s -= LARGE_PAGE_SIZE_4M;
13027e23b5fSChristophe Leroy }
13127e23b5fSChristophe Leroy
13227e23b5fSChristophe Leroy mapped = total_lowmem - s;
13327e23b5fSChristophe Leroy
13427e23b5fSChristophe Leroy /* If the size of RAM is not an exact power of two, we may not
13527e23b5fSChristophe Leroy * have covered RAM in its entirety with 16 and 4 MiB
13627e23b5fSChristophe Leroy * pages. Consequently, restrict the top end of RAM currently
13727e23b5fSChristophe Leroy * allocable so that calls to the MEMBLOCK to allocate PTEs for "tail"
13827e23b5fSChristophe Leroy * coverage with normal-sized pages (or other reasons) do not
13927e23b5fSChristophe Leroy * attempt to allocate outside the allowed range.
14027e23b5fSChristophe Leroy */
14127e23b5fSChristophe Leroy memblock_set_current_limit(mapped);
14227e23b5fSChristophe Leroy
14327e23b5fSChristophe Leroy return mapped;
14427e23b5fSChristophe Leroy }
14527e23b5fSChristophe Leroy
setup_initial_memory_limit(phys_addr_t first_memblock_base,phys_addr_t first_memblock_size)14627e23b5fSChristophe Leroy void setup_initial_memory_limit(phys_addr_t first_memblock_base,
14727e23b5fSChristophe Leroy phys_addr_t first_memblock_size)
14827e23b5fSChristophe Leroy {
14927e23b5fSChristophe Leroy /* We don't currently support the first MEMBLOCK not mapping 0
15027e23b5fSChristophe Leroy * physical on those processors
15127e23b5fSChristophe Leroy */
15227e23b5fSChristophe Leroy BUG_ON(first_memblock_base != 0);
15327e23b5fSChristophe Leroy
15427e23b5fSChristophe Leroy /* 40x can only access 16MB at the moment (see head_40x.S) */
15527e23b5fSChristophe Leroy memblock_set_current_limit(min_t(u64, first_memblock_size, 0x00800000));
15627e23b5fSChristophe Leroy }
157