Searched refs:SPI_CTR_CFG_REG (Results 1 – 3 of 3) sorted by relevance
| /openbmc/qemu/hw/ssi/ |
| H A D | pnv_spi.c | 285 s->N1_bits = GETFIELD(SPI_CTR_CFG_N1, s->regs[SPI_CTR_CFG_REG]); in calculate_N1()
314 s->regs[SPI_CTR_CFG_REG]) == 0) { in calculate_N1()
319 s->regs[SPI_CTR_CFG_REG]) == 1) { in calculate_N1()
476 (GETFIELD(SPI_CTR_CFG_N2_CTRL_B0, s->regs[SPI_CTR_CFG_REG]) == 1)) { in operation_shiftn1()
530 s->N2_bits = GETFIELD(SPI_CTR_CFG_N2, s->regs[SPI_CTR_CFG_REG]); in calculate_N2()
556 s->regs[SPI_CTR_CFG_REG]) == 0) { in calculate_N2()
561 s->regs[SPI_CTR_CFG_REG]) == 1) { in calculate_N2()
973 GETFIELD(SPI_CTR_CFG_CMP1, s->regs[SPI_CTR_CFG_REG])) { in operation_sequencer()
992 s->regs[SPI_CTR_CFG_REG]); in operation_sequencer()
1090 case SPI_CTR_CFG_REG: in pnv_spi_xscom_read()
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| /openbmc/qemu/tests/qtest/ |
| H A D | pnv-spi-seeprom-test.c | 54 pnv_spi_xscom_write(qts, chip, SPI_CTR_CFG_REG, READ_OP_COUNTER_CONFIG); in spi_seeprom_transaction()
68 pnv_spi_xscom_write(qts, chip, SPI_CTR_CFG_REG, WRITE_OP_COUNTER_CONFIG); in spi_seeprom_transaction()
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| /openbmc/qemu/include/hw/ssi/ |
| H A D | pnv_spi_regs.h | 30 #define SPI_CTR_CFG_REG 0x01 macro
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