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Searched refs:SOR0_CLK_SEL0 (Results 1 – 2 of 2) sorted by relevance

/openbmc/u-boot/arch/arm/include/asm/arch-tegra124/
H A Dclock.h22 #define SOR0_CLK_SEL0 (1 << 14) macro
/openbmc/u-boot/arch/arm/mach-tegra/tegra124/
H A Dclock.c1047 setbits_le32(reg, SOR0_CLK_SEL0); in clock_sor_enable_edp_clock()