Searched refs:SOC_REGS_PHY_BASE (Results 1 – 7 of 7) sorted by relevance
48 #define SOC_REGS_PHY_BASE 0xd0000000 macro50 #define SOC_REGS_PHY_BASE 0xf0000000 macro52 #define SOC_REGS_PHY_BASE 0xf1000000 macro54 #define MVEBU_REGISTER(x) (SOC_REGS_PHY_BASE + x)
56 pregs.regs[1] = SOC_REGS_PHY_BASE; in a8k_dram_scan_ap_sz()
397 writel(SOC_REGS_PHY_BASE, INTREG_BASE_ADDR_REG); in arch_cpu_init()398 set_cbar(SOC_REGS_PHY_BASE + 0xC000); in arch_cpu_init()
17 #define INTER_REGS_BASE SOC_REGS_PHY_BASE
317 writel(SOC_REGS_PHY_BASE, pcie->base + PCIE_BAR_LO_OFF(0)); in mvebu_pcie_probe()345 pcie->base = (void *)(fdt32_to_cpu(addr[2]) + SOC_REGS_PHY_BASE); in mvebu_pcie_port_parse_dt()
78 #define INTER_REGS_BASE SOC_REGS_PHY_BASE