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Searched refs:SOCFPGA_SDR_ADDRESS (Results 1 – 8 of 8) sorted by relevance

/openbmc/u-boot/drivers/ddr/altera/
H A Dsdram_s10.c57 return readl((void __iomem *)SOCFPGA_SDR_ADDRESS + (reg)); in hmc_ecc_readl()
62 return writel(data, (void __iomem *)SOCFPGA_SDR_ADDRESS + (reg)); in hmc_ecc_writel()
86 return wait_for_bit_le32((const void *)(SOCFPGA_SDR_ADDRESS + in emif_clear()
112 ret = wait_for_bit_le32((const void *)(SOCFPGA_SDR_ADDRESS + in emif_reset()
203 ret = wait_for_bit_le32((const void *)(SOCFPGA_SDR_ADDRESS + in sdram_mmr_init_full()
344 setbits_le32(SOCFPGA_SDR_ADDRESS + ECCCTRL1, in sdram_mmr_init_full()
348 clrbits_le32(SOCFPGA_SDR_ADDRESS + ECCCTRL1, in sdram_mmr_init_full()
351 setbits_le32(SOCFPGA_SDR_ADDRESS + ECCCTRL2, in sdram_mmr_init_full()
355 clrbits_le32(SOCFPGA_SDR_ADDRESS + ECCCTRL1, in sdram_mmr_init_full()
359 clrbits_le32(SOCFPGA_SDR_ADDRESS + ECCCTRL2, in sdram_mmr_init_full()
H A Dsequencer.h83 #define SDR_PHYGRP_SCCGRP_ADDRESS (SOCFPGA_SDR_ADDRESS | 0x0)
84 #define SDR_PHYGRP_PHYMGRGRP_ADDRESS (SOCFPGA_SDR_ADDRESS | 0x1000)
85 #define SDR_PHYGRP_RWMGRGRP_ADDRESS (SOCFPGA_SDR_ADDRESS | 0x2000)
86 #define SDR_PHYGRP_DATAMGRGRP_ADDRESS (SOCFPGA_SDR_ADDRESS | 0x4000)
87 #define SDR_PHYGRP_REGFILEGRP_ADDRESS (SOCFPGA_SDR_ADDRESS | 0x4800)
H A Dsdram_arria10.c45 (void *)SOCFPGA_SDR_ADDRESS;
/openbmc/u-boot/arch/arm/mach-socfpga/include/mach/
H A Dbase_addr_s10.h12 #define SOCFPGA_SDR_ADDRESS 0xf8011000 macro
H A Dbase_addr_a10.h42 #define SOCFPGA_SDR_ADDRESS 0xffcfb000 macro
H A Dbase_addr_ac5.h30 #define SOCFPGA_SDR_ADDRESS 0xffc20000 macro
H A Dsdram_gen5.h22 #define SDR_CTRLGRP_ADDRESS (SOCFPGA_SDR_ADDRESS | 0x5000)
/openbmc/u-boot/drivers/fpga/
H A Dsocfpga_gen5.c221 writel(0, SOCFPGA_SDR_ADDRESS + SDR_CTRLGRP_FPGAPORTRST_ADDRESS); in socfpga_load()