Home
last modified time | relevance | path

Searched refs:SOCFPGA_RESET (Results 1 – 11 of 11) sorted by relevance

/openbmc/u-boot/arch/arm/mach-socfpga/
H A Dspl_gen5.c41 socfpga_per_reset(SOCFPGA_RESET(NAND), 0); in spl_boot_device()
45 socfpga_per_reset(SOCFPGA_RESET(SDMMC), 0); in spl_boot_device()
46 socfpga_per_reset(SOCFPGA_RESET(DMA), 0); in spl_boot_device()
50 socfpga_per_reset(SOCFPGA_RESET(QSPI), 0); in spl_boot_device()
159 socfpga_per_reset(SOCFPGA_RESET(SDR), 0); in board_init_f()
160 socfpga_per_reset(SOCFPGA_RESET(UART0), 0); in board_init_f()
161 socfpga_per_reset(SOCFPGA_RESET(OSC1TIMER0), 0); in board_init_f()
193 socfpga_per_reset(SOCFPGA_RESET(UART0), 0); in board_init_f()
H A Dspl_a10.c41 socfpga_per_reset(SOCFPGA_RESET(NAND), 0); in spl_boot_device()
45 socfpga_per_reset(SOCFPGA_RESET(SDMMC), 0); in spl_boot_device()
46 socfpga_per_reset(SOCFPGA_RESET(DMA), 0); in spl_boot_device()
50 socfpga_per_reset(SOCFPGA_RESET(QSPI), 0); in spl_boot_device()
H A Dspl_s10.c128 socfpga_per_reset(SOCFPGA_RESET(L4WD0), 1); in board_init_f()
129 socfpga_per_reset(SOCFPGA_RESET(L4WD0), 0); in board_init_f()
136 socfpga_per_reset(SOCFPGA_RESET(OSC1TIMER0), 0); in board_init_f()
145 socfpga_per_reset(SOCFPGA_RESET(UART0), 0); in board_init_f()
H A Dmisc.c119 socfpga_per_reset(SOCFPGA_RESET(L4WD0), 1); in arch_cpu_init()
120 socfpga_per_reset(SOCFPGA_RESET(L4WD0), 0); in arch_cpu_init()
H A Dmisc_gen5.c206 socfpga_per_reset(SOCFPGA_RESET(SPIM0), 0); in arch_early_init_r()
207 socfpga_per_reset(SOCFPGA_RESET(SPIM1), 0); in arch_early_init_r()
211 socfpga_per_reset(SOCFPGA_RESET(NAND), 0); in arch_early_init_r()
H A Dreset_manager_arria10.c164 const u32 l4wd0 = (1 << RSTMGR_RESET(SOCFPGA_RESET(L4WD0)) | in socfpga_per_reset_all()
165 (1 << RSTMGR_RESET(SOCFPGA_RESET(L4SYSTIMER0)))); in socfpga_per_reset_all()
H A Dreset_manager_gen5.c58 const u32 l4wd0 = 1 << RSTMGR_RESET(SOCFPGA_RESET(L4WD0)); in socfpga_per_reset_all()
H A Dreset_manager_s10.c49 const u32 l4wd0 = 1 << RSTMGR_RESET(SOCFPGA_RESET(L4WD0)); in socfpga_per_reset_all()
/openbmc/u-boot/arch/arm/mach-socfpga/include/mach/
H A Dreset_manager.h37 #define SOCFPGA_RESET(_name) RSTMGR_##_name macro
H A Dreset_manager_s10.h112 #define SOCFPGA_RESET(_name) RSTMGR_##_name macro
/openbmc/u-boot/drivers/ddr/altera/
H A Dsdram_s10.c199 socfpga_per_reset(SOCFPGA_RESET(SDR), 0); in sdram_mmr_init_full()