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Searched refs:SMMU (Results 1 – 20 of 20) sorted by relevance

/openbmc/linux/Documentation/devicetree/bindings/iommu/
H A Dnvidia,tegra30-smmu.txt1 NVIDIA Tegra 30 IOMMU H/W, SMMU (System Memory Management Unit)
6 of the SMMU register blocks.
10 - nvidia,ahb : phandle to the ahb bus connected to SMMU.
H A Dmsm,iommu-v0.txt18 - clocks : List of clocks to be used during SMMU register access. See
/openbmc/linux/Documentation/ABI/testing/
H A Dsysfs-bus-platform-devices-ampere-smpro93 …| SMMU (other) | 6 | TCU | 100 | RC # …
95 …| SMMU (other) | 6 | TBU0 | 0 | RC # …
97 …| SMMU (other) | 6 | TBU1 | 1 | RC # …
99 …| SMMU (other) | 6 | TBU2 | 2 | RC # …
101 …| SMMU (other) | 6 | TBU3 | 3 | RC # …
103 …| SMMU (other) | 6 | TBU4 | 4 | RC # …
105 …| SMMU (other) | 6 | TBU5 | 5 | RC # …
107 …| SMMU (other) | 6 | TBU6 | 6 | RC # …
109 …| SMMU (other) | 6 | TBU7 | 7 | RC # …
111 …| SMMU (other) | 6 | TBU8 | 8 | RC # …
[all …]
/openbmc/qemu/tests/avocado/
H A Dsmmu.py17 class SMMU(LinuxTest): class
42 super(SMMU, self).setUp(None, 'virtio-net-pci' + self.IOMMU_ADDON)
/openbmc/linux/drivers/iommu/
H A DKconfig251 bool "NVIDIA Tegra SMMU Support"
257 This driver supports the IOMMU hardware (SMMU) found on NVIDIA Tegra
322 tristate "ARM Ltd. System MMU (SMMU) Support"
333 the ARM SMMU architecture.
341 to the SMMU but does not provide any support via the DMA API.
348 bool "Default to disabling bypass on ARM SMMU v1 and v2"
355 will not be allowed to pass through the SMMU.
378 of the ARM SMMU, this needs to be built into the SMMU driver.
381 bool "ARM SMMU QCOM implementation defined debug support"
384 Support for implementation specific debug features in ARM SMMU
/openbmc/linux/arch/arm64/boot/dts/qcom/
H A Dmsm8996pro-xiaomi-scorpio.dts35 /* DSI0 and MDP SMMU clocks */
102 * Probing this SMMU causes a crash due to writing to some secure
110 * MDSS depends on the MDP SMMU, and probing it alters the bootloader
H A Dsdm845-cheza.dtsi786 * GPU to update the SMMU pagetables for context switches. Work
H A Dsdm630.dtsi1119 * GX GDSC parent is CX. We need to bring up CX for SMMU
H A Dmsm8998.dtsi1584 * GPU-CX for SMMU but we need both of them up for Adreno.
/openbmc/linux/Documentation/arch/arm64/
H A Dsilicon-errata.rst245 | Hisilicon | Hip08 SMMU PMCG | #162001800 | N/A |
249 | | SMMU PMCG | | |
H A Dacpi_object_usage.rst244 when using GICv3-ITS and an SMMU); on SBSA Level 0 platforms, it
522 attributes; the presence of an SMMU can be used to
525 the appropriate SMMU configuration (see Table 17 of
/openbmc/linux/Documentation/userspace-api/
H A Diommu.rst26 2. Bind/Unbind guest PASID table (e.g. ARM SMMU)
36 2. Multiple vendors (Intel VT-d, ARM SMMU, etc.)
/openbmc/linux/Documentation/misc-devices/
H A Duacce.rst148 * Support device page faults (PCI PRI or SMMU Stall)
/openbmc/linux/drivers/perf/
H A DKconfig100 through the SMMU and allow the resulting information to be filtered
/openbmc/linux/arch/arm64/boot/dts/hisilicon/
H A Dhip06.dtsi333 * have a SMMU translation for MSI. In order to workaround this,
H A Dhip07.dtsi1188 * have a SMMU translation for MSI. In order to workaround this,
/openbmc/linux/arch/arm64/boot/dts/arm/
H A Djuno-base.dtsi664 /* The SMMU is only really of interest to bare-metal hypervisors */
/openbmc/qemu/docs/system/arm/
H A Dcpu-features.rst448 only support RME within the CPU proper, not within the SMMU or GIC.
/openbmc/qemu/
H A DMAINTAINERS212 ARM SMMU
/openbmc/linux/
H A DMAINTAINERS1758 ARM SMMU DRIVERS