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Searched refs:SIUL2_MSCRn (Results 1 – 3 of 3) sorted by relevance

/openbmc/u-boot/board/freescale/s32v234evb/
H A Ds32v234evb.c95 writel(SIUL2_USDHC_PAD_CTRL_CLK, SIUL2_MSCRn(150)); in board_mmc_init()
96 writel(0x3, SIUL2_MSCRn(902)); in board_mmc_init()
100 writel(0x3, SIUL2_MSCRn(901)); in board_mmc_init()
104 writel(0x3, SIUL2_MSCRn(903)); in board_mmc_init()
108 writel(0x3, SIUL2_MSCRn(904)); in board_mmc_init()
112 writel(0x3, SIUL2_MSCRn(905)); in board_mmc_init()
116 writel(0x3, SIUL2_MSCRn(906)); in board_mmc_init()
120 writel(0x3, SIUL2_MSCRn(907)); in board_mmc_init()
124 writel(0x3, SIUL2_MSCRn(908)); in board_mmc_init()
128 writel(0x3, SIUL2_MSCRn(909)); in board_mmc_init()
[all …]
H A Dlpddr2.c20 mscr_offset_ck0 = SIUL2_MSCRn(_DDR0_CKE0); in lpddr2_config_iomux()
21 writel(LPDDR2_CLK0_PAD, SIUL2_MSCRn(_DDR0_CLK0)); in lpddr2_config_iomux()
23 writel(LPDDR2_CKEn_PAD, SIUL2_MSCRn(_DDR0_CKE0)); in lpddr2_config_iomux()
30 writel(LPDDR2_DMn_PAD, SIUL2_MSCRn(i)); in lpddr2_config_iomux()
33 writel(LPDDR2_DQSn_PAD, SIUL2_MSCRn(i)); in lpddr2_config_iomux()
36 writel(LPDDR2_An_PAD, SIUL2_MSCRn(i)); in lpddr2_config_iomux()
39 writel(LPDDR2_Dn_PAD, SIUL2_MSCRn(i)); in lpddr2_config_iomux()
51 writel(LPDDR2_DMn_PAD, SIUL2_MSCRn(i)); in lpddr2_config_iomux()
54 writel(LPDDR2_DQSn_PAD, SIUL2_MSCRn(i)); in lpddr2_config_iomux()
57 writel(LPDDR2_An_PAD, SIUL2_MSCRn(i)); in lpddr2_config_iomux()
[all …]
/openbmc/u-boot/arch/arm/include/asm/arch-s32v234/
H A Dsiul.h29 #define SIUL2_MSCRn(i) (SIUL2_MSCR_BASE + 4 * (i)) macro