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Searched refs:SET_BIT (Results 1 – 20 of 20) sorted by relevance

/openbmc/linux/drivers/net/ethernet/sfc/
H A Dmcdi_port_common.c120 SET_BIT(Backplane); in mcdi_to_ethtool_linkset()
132 SET_BIT(FIBRE); in mcdi_to_ethtool_linkset()
159 SET_BIT(TP); in mcdi_to_ethtool_linkset()
161 SET_BIT(10baseT_Half); in mcdi_to_ethtool_linkset()
163 SET_BIT(10baseT_Full); in mcdi_to_ethtool_linkset()
165 SET_BIT(100baseT_Half); in mcdi_to_ethtool_linkset()
167 SET_BIT(100baseT_Full); in mcdi_to_ethtool_linkset()
178 SET_BIT(Pause); in mcdi_to_ethtool_linkset()
180 SET_BIT(Asym_Pause); in mcdi_to_ethtool_linkset()
182 SET_BIT(Autoneg); in mcdi_to_ethtool_linkset()
[all …]
/openbmc/linux/drivers/net/ethernet/sfc/siena/
H A Dmcdi_port_common.c121 SET_BIT(Backplane); in mcdi_to_ethtool_linkset()
133 SET_BIT(FIBRE); in mcdi_to_ethtool_linkset()
160 SET_BIT(TP); in mcdi_to_ethtool_linkset()
162 SET_BIT(10baseT_Half); in mcdi_to_ethtool_linkset()
164 SET_BIT(10baseT_Full); in mcdi_to_ethtool_linkset()
166 SET_BIT(100baseT_Half); in mcdi_to_ethtool_linkset()
168 SET_BIT(100baseT_Full); in mcdi_to_ethtool_linkset()
179 SET_BIT(Pause); in mcdi_to_ethtool_linkset()
181 SET_BIT(Asym_Pause); in mcdi_to_ethtool_linkset()
183 SET_BIT(Autoneg); in mcdi_to_ethtool_linkset()
[all …]
/openbmc/linux/drivers/video/fbdev/kyro/
H A DSTG4000VTG.c34 tmp |= SET_BIT(8); in DisableVGA()
43 tmp = (STG_READ_REG(DACSyncCtrl)) | SET_BIT(0) | SET_BIT(2); in StopVTG()
53 tmp = ((STG_READ_REG(DACSyncCtrl)) | SET_BIT(31)); in StartVTG()
157 tmp = STG_READ_REG(DACSyncCtrl) | SET_BIT(3) | SET_BIT(1); in SetupVTG()
H A DSTG4000Ramdac.c104 tmp &= ~SET_BIT(31); in InitialiseRamdac()
152 tmp = (STG_READ_REG(DACStreamCtrl)) & ~SET_BIT(0); in DisableRamdacOutput()
161 tmp = (STG_READ_REG(DACStreamCtrl)) | SET_BIT(0); in EnableRamdacOutput()
H A DSTG4000InitDevice.c296 tmp |= SET_BIT(14); in SetCoreClockPLL()
306 tmp |= SET_BIT(14); in SetCoreClockPLL()
314 tmp = ((STG_READ_REG(Thread0Enable)) | SET_BIT(0)); in SetCoreClockPLL()
318 tmp = ((STG_READ_REG(Thread1Enable)) | SET_BIT(0)); in SetCoreClockPLL()
H A DSTG4000OverlayDevice.c181 tmp |= SET_BIT(31); /* Overlay format to Planer */ in CreateOverlaySurface()
293 tmp |= SET_BIT(7); in EnableOverlayPlane()
298 tmp |= SET_BIT(1); /* video stream */ in EnableOverlayPlane()
H A DSTG4000Reg.h31 #define SET_BIT(n) (1<<(n)) macro
/openbmc/u-boot/arch/mips/mach-ath79/ar933x/
H A Dlowlevel_init.S14 #define SET_BIT(val, bit) ((val) | (1 << (bit))) macro
15 #define SET_PLL_PD(val) SET_BIT(val, 30)
16 #define AHB_DIV_TO_4(val) SET_BIT(SET_BIT(val, 15), 16)
17 #define PLL_BYPASS(val) SET_BIT(val, 2)
/openbmc/linux/drivers/net/ethernet/apm/xgene/
H A Dxgene_enet_ring2.c19 ring_cfg[3] |= SET_BIT(X2_DEQINTEN); in xgene_enet_ring_init()
31 ring_cfg[5] |= SET_BIT(X2_QBASE_AM) | SET_BIT(X2_MSG_AM); in xgene_enet_ring_init()
H A Dxgene_enet_main.c106 SET_BIT(COHERENT)); in xgene_enet_refill_pagepool()
157 SET_BIT(COHERENT)); in xgene_enet_refill_bufpool()
360 *hopinfo |= SET_BIT(ET) | SET_VAL(MSS, mss_index); in xgene_enet_work_msg()
373 SET_BIT(IC) | in xgene_enet_work_msg()
374 SET_BIT(TYPE_ETH_WORK_MESSAGE); in xgene_enet_work_msg()
447 SET_BIT(COHERENT)); in xgene_enet_setup_tx_desc()
/openbmc/linux/drivers/usb/storage/
H A Drealtek_cr.c120 #define SET_BIT(data, idx) ((data) |= 1 << (idx)) macro
574 SET_BIT(value, 2); in config_autodelink_after_power_on()
579 SET_BIT(value, 7); in config_autodelink_after_power_on()
592 SET_BIT(value, 2); in config_autodelink_after_power_on()
639 SET_BIT(value, 2); in config_autodelink_before_power_down()
655 SET_BIT(value, 0); in config_autodelink_before_power_down()
657 SET_BIT(value, 2); in config_autodelink_before_power_down()
671 SET_BIT(value, 0); in config_autodelink_before_power_down()
672 SET_BIT(value, 7); in config_autodelink_before_power_down()
676 SET_BIT(value, 2); in config_autodelink_before_power_down()
/openbmc/linux/drivers/scsi/sym53c8xx_2/
H A Dsym_nvram.c235 #define SET_BIT 0 macro
248 case SET_BIT: in S24C16_set_bit()
272 S24C16_set_bit(np, 1, gpreg, SET_BIT); in S24C16_start()
284 S24C16_set_bit(np, 1, gpreg, SET_BIT); in S24C16_stop()
294 S24C16_set_bit(np, write_bit, gpreg, SET_BIT); in S24C16_do_bit()
488 #undef SET_BIT
/openbmc/linux/include/linux/mdio/
H A Dmdio-xgene.h111 #define SET_BIT(field) \ macro
/openbmc/linux/drivers/crypto/intel/qat/qat_common/
H A Dqat_hal.c154 #define SET_BIT(wrd, bit) ((wrd) | 1 << (bit)) macro
170 SET_BIT(csr, CE_INUSE_CONTEXTS_BITPOS) : in qat_hal_set_ae_ctx_mode()
185 SET_BIT(csr, CE_NN_MODE_BITPOS) : in qat_hal_set_ae_nn_mode()
205 SET_BIT(csr, CE_LMADDR_0_GLOBAL_BITPOS) : in qat_hal_set_ae_lm_mode()
210 SET_BIT(csr, CE_LMADDR_1_GLOBAL_BITPOS) : in qat_hal_set_ae_lm_mode()
215 SET_BIT(csr, CE_LMADDR_2_GLOBAL_BITPOS) : in qat_hal_set_ae_lm_mode()
220 SET_BIT(csr, CE_LMADDR_3_GLOBAL_BITPOS) : in qat_hal_set_ae_lm_mode()
241 SET_BIT(csr, CE_T_INDEX_GLOBAL_BITPOS) : in qat_hal_set_ae_tindex_mode()
/openbmc/u-boot/arch/arm/mach-mvebu/serdes/a38x/
H A Dhigh_speed_env_spec.h15 #define SET_BIT(data, bit) ((data) | (0x1 << (bit))) macro
H A Dhigh_speed_env_spec.c1406 data = SET_BIT(data, 9); in hws_pre_serdes_init_config()
1464 data = SET_BIT(data, bit_off); in serdes_polarity_config()
/openbmc/linux/drivers/staging/rts5208/
H A Drtsx_chip.h325 #define SET_BIT(data, idx) ((data) |= 1 << (idx)) macro
H A Drtsx_scsi.c421 SET_BIT(chip->lun_mc, lun); in test_unit_ready()
857 SET_BIT(chip->lun_mc, lun); in read_write()
1058 SET_BIT(chip->lun_mc, lun); in read_capacity()
H A Dsd.c3770 SET_BIT(chip->lun_mc, lun);
/openbmc/linux/drivers/i2c/busses/
H A Di2c-qup.c120 #define SET_BIT 0x1 macro