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Searched refs:SDRAM_CFG_DBW_MASK (Results 1 – 7 of 7) sorted by relevance

/openbmc/u-boot/board/freescale/p1010rdb/
H A Dddr.c133 ddr_cfg_regs.ddr_sdram_cfg &= ~SDRAM_CFG_DBW_MASK; in fixed_sdram()
/openbmc/u-boot/arch/powerpc/cpu/mpc83xx/
H A Dspd_sdram.c35 if ((ddr->sdram_cfg & SDRAM_CFG_DBW_MASK) == SDRAM_CFG_DBW_16) in board_add_ram_info()
37 else if ((ddr->sdram_cfg & SDRAM_CFG_DBW_MASK) == SDRAM_CFG_DBW_32) in board_add_ram_info()
/openbmc/u-boot/include/
H A Dfsl_ddr_sdram.h115 #define SDRAM_CFG_DBW_MASK 0x00180000 macro
H A Dmpc83xx.h1243 #define SDRAM_CFG_DBW_MASK 0x00180000 macro
/openbmc/u-boot/drivers/ddr/fsl/
H A Darm_ddr_gen3.c222 bus_width = 3 - ((ddr_in32(&ddr->sdram_cfg) & SDRAM_CFG_DBW_MASK) in fsl_ddr_set_memctl_regs()
H A Dmpc85xx_ddr_gen3.c420 bus_width = 3 - ((ddr->sdram_cfg & SDRAM_CFG_DBW_MASK) in fsl_ddr_set_memctl_regs()
H A Dfsl_ddr_gen4.c457 bus_width = 3 - ((ddr_in32(&ddr->sdram_cfg) & SDRAM_CFG_DBW_MASK) in fsl_ddr_set_memctl_regs()