Searched refs:SDCDIV (Results 1 – 3 of 3) sorted by relevance
| /openbmc/u-boot/drivers/mmc/ |
| H A D | bcm2835_sdhost.c | 51 #define SDCDIV 0x0c /* Start value for clock divider - 11 R/W */ macro
188 dev_dbg(dev, "SDCDIV 0x%08x\n", readl(host->ioaddr + SDCDIV)); in bcm2835_dumpregs()
211 writel(0, host->ioaddr + SDCDIV); in bcm2835_reset_internal()
232 writel(host->cdiv, host->ioaddr + SDCDIV); in bcm2835_reset_internal()
622 writel(host->cdiv, host->ioaddr + SDCDIV); in bcm2835_set_clock()
645 writel(host->cdiv, host->ioaddr + SDCDIV); in bcm2835_set_clock()
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| /openbmc/qemu/hw/sd/ |
| H A D | bcm2835_sdhost.c | 32 #define SDCDIV 0x0c /* Start value for clock divider - 11 R/W */ in DECLARE_INSTANCE_CHECKER() macro
330 case SDCDIV: in bcm2835_sdhost_write()
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| /openbmc/linux/drivers/mmc/host/ |
| H A D | bcm2835.c | 55 #define SDCDIV 0x0c /* Start value for clock divider - 11 R/W */ macro
228 dev_dbg(dev, "SDCDIV 0x%08x\n", readl(host->ioaddr + SDCDIV)); in bcm2835_dumpregs()
250 writel(0, host->ioaddr + SDCDIV); in bcm2835_reset_internal()
268 writel(host->cdiv, host->ioaddr + SDCDIV); in bcm2835_reset_internal()
1123 writel(host->cdiv, host->ioaddr + SDCDIV); in bcm2835_set_clock()
1146 writel(host->cdiv, host->ioaddr + SDCDIV); in bcm2835_set_clock()
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