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Searched refs:SCLK_RTC32K (Results 1 – 9 of 9) sorted by relevance

/openbmc/linux/include/dt-bindings/clock/
H A Drk3308-cru.h19 #define SCLK_RTC32K 15 macro
H A Drk3328-cru.h19 #define SCLK_RTC32K 30 macro
/openbmc/u-boot/include/dt-bindings/clock/
H A Drk3328-cru.h18 #define SCLK_RTC32K 30 macro
/openbmc/u-boot/drivers/clk/rockchip/
H A Dclk_rk3328.c616 case SCLK_RTC32K: in rk3328_clk_set_rate()
737 case SCLK_RTC32K: in rk3328_clk_set_parent()
/openbmc/linux/arch/arm64/boot/dts/rockchip/
H A Drk3328.dtsi732 <&cru SCLK_RTC32K>;
800 <&cru SCLK_RTC32K>, <&cru SCLK_UART0>,
814 <&cru SCLK_RTC32K>;
H A Drk3308.dtsi755 assigned-clocks = <&cru SCLK_RTC32K>;
/openbmc/u-boot/arch/arm/dts/
H A Drk3328.dtsi368 <&cru SCLK_RTC32K>, <&cru SCLK_UART0>,
390 <&cru SCLK_RTC32K>, <&cru SCLK_USB3OTG_SUSPEND>;
/openbmc/linux/drivers/clk/rockchip/
H A Dclk-rk3328.c271 COMPOSITE(SCLK_RTC32K, "clk_rtc32k", mux_2plls_xin24m_p, 0,
H A Dclk-rk3308.c223 MUX(SCLK_RTC32K, "clk_rtc32k", mux_rtc32k_p, CLK_SET_RATE_PARENT,