| /openbmc/u-boot/include/dt-bindings/clock/ |
| H A D | rk3128-cru.h | 32 #define SCLK_OTGPHY0 93 macro
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| H A D | rk3036-cru.h | 32 #define SCLK_OTGPHY0 93 macro
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| H A D | rk3188-cru-common.h | 37 #define SCLK_OTGPHY0 81 macro
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| H A D | rk3288-cru.h | 45 #define SCLK_OTGPHY0 93 macro
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| H A D | rk3368-cru.h | 54 #define SCLK_OTGPHY0 93 macro
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| /openbmc/linux/include/dt-bindings/clock/ |
| H A D | rk3036-cru.h | 32 #define SCLK_OTGPHY0 93 macro
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| H A D | rk3188-cru-common.h | 37 #define SCLK_OTGPHY0 81 macro
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| H A D | rk3128-cru.h | 56 #define SCLK_OTGPHY0 142 macro
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| H A D | rk3228-cru.h | 65 #define SCLK_OTGPHY0 142 macro
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| H A D | rk3288-cru.h | 48 #define SCLK_OTGPHY0 93 macro
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| H A D | rk3368-cru.h | 44 #define SCLK_OTGPHY0 93 macro
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| /openbmc/linux/drivers/clk/rockchip/ |
| H A D | clk-rk3036.c | 329 GATE(SCLK_OTGPHY0, "sclk_otgphy0", "xin12m", CLK_IGNORE_UNUSED,
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| H A D | clk-rk3128.c | 385 GATE(SCLK_OTGPHY0, "sclk_otgphy0", "xin12m", 0,
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| H A D | clk-rk3228.c | 461 GATE(SCLK_OTGPHY0, "sclk_otgphy0", "xin24m", 0,
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| H A D | clk-rk3188.c | 349 GATE(SCLK_OTGPHY0, "sclk_otgphy0", "xin24m", CLK_IGNORE_UNUSED,
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| H A D | clk-rk3368.c | 565 GATE(SCLK_OTGPHY0, "sclk_otgphy0", "xin24m", CLK_IGNORE_UNUSED,
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| H A D | clk-rk3288.c | 558 GATE(SCLK_OTGPHY0, "sclk_otgphy0", "xin24m", CLK_IGNORE_UNUSED,
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| /openbmc/u-boot/arch/arm/dts/ |
| H A D | rk3188.dtsi | 141 clocks = <&cru SCLK_OTGPHY0>;
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| H A D | rk3128.dtsi | 384 clocks = <&cru SCLK_OTGPHY0>;
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| H A D | rk3288-veyron.dtsi | 831 assigned-clock-parents = <&cru SCLK_OTGPHY0>;
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| H A D | rk3288.dtsi | 952 clocks = <&cru SCLK_OTGPHY0>;
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| /openbmc/linux/arch/arm/boot/dts/rockchip/ |
| H A D | rk3188.dtsi | 657 clocks = <&cru SCLK_OTGPHY0>;
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| H A D | rk3066a.dtsi | 693 clocks = <&cru SCLK_OTGPHY0>;
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| H A D | rk3128.dtsi | 208 clocks = <&cru SCLK_OTGPHY0>;
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| H A D | rk322x.dtsi | 255 clocks = <&cru SCLK_OTGPHY0>;
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