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Searched refs:RVD (Results 1 – 11 of 11) sorted by relevance

/openbmc/qemu/target/riscv/insn_trans/
H A Dtrans_rvzfa.c.inc85 REQUIRE_EXT(ctx, RVD);
218 REQUIRE_EXT(ctx, RVD);
235 REQUIRE_EXT(ctx, RVD);
320 REQUIRE_EXT(ctx, RVD);
337 REQUIRE_EXT(ctx, RVD);
388 REQUIRE_EXT(ctx, RVD);
407 REQUIRE_EXT(ctx, RVD);
422 REQUIRE_EXT(ctx, RVD);
467 REQUIRE_EXT(ctx, RVD);
482 REQUIRE_EXT(ctx, RVD);
H A Dtrans_rvd.c.inc23 REQUIRE_EXT(ctx, RVD); \
36 if (!has_ext(ctx, RVD) || !has_ext(ctx, RVC)) { \
47 REQUIRE_EXT(ctx, RVD);
62 REQUIRE_EXT(ctx, RVD);
524 REQUIRE_EXT(ctx, RVD);
574 REQUIRE_EXT(ctx, RVD);
H A Dtrans_xthead.c.inc381 REQUIRE_EXT(ctx, RVD);
397 REQUIRE_EXT(ctx, RVD);
413 REQUIRE_EXT(ctx, RVD);
429 REQUIRE_EXT(ctx, RVD);
448 REQUIRE_EXT(ctx, RVD);
464 REQUIRE_EXT(ctx, RVD);
H A Dtrans_rvv.c.inc2216 * RVF and RVD can be treated equally.
/openbmc/qemu/target/riscv/tcg/
H A Dtcg-cpu.c289 riscv_has_ext(env, RVD) && in riscv_cpu_validate_set_extensions()
308 env->misa_ext |= RVI | RVM | RVA | RVF | RVD; in riscv_cpu_validate_set_extensions()
309 env->misa_ext_mask |= RVI | RVM | RVA | RVF | RVD; in riscv_cpu_validate_set_extensions()
370 if (riscv_has_ext(env, RVD) && !riscv_has_ext(env, RVF)) { in riscv_cpu_validate_set_extensions()
396 if (cpu->cfg.ext_zve64d && !riscv_has_ext(env, RVD)) { in riscv_cpu_validate_set_extensions()
473 if (riscv_has_ext(env, RVD)) { in riscv_cpu_validate_set_extensions()
488 if (!riscv_has_ext(env, RVD) && cpu->cfg.ext_zcd) { in riscv_cpu_validate_set_extensions()
783 MISA_CFG(RVD, true),
/openbmc/qemu/target/riscv/
H A Dgdbstub.c112 if (env->misa_ext & RVD) { in riscv_gdb_get_fpu()
315 if (env->misa_ext & RVD) { in riscv_cpu_register_gdb_regs_for_features()
H A Dcpu.c42 const uint32_t misa_bits[] = {RVI, RVE, RVM, RVA, RVF, RVD, RVV,
382 riscv_cpu_set_misa(env, MXL_RV32, RVI | RVM | RVA | RVF | RVD | RVC | RVU); in riscv_any_cpu_init()
384 riscv_cpu_set_misa(env, MXL_RV64, RVI | RVM | RVA | RVF | RVD | RVC | RVU); in riscv_any_cpu_init()
437 RVI | RVM | RVA | RVF | RVD | RVC | RVS | RVU); in rv64_sifive_u_cpu_init()
573 RVI | RVM | RVA | RVF | RVD | RVC | RVS | RVU); in rv32_sifive_u_cpu_init()
1246 MISA_EXT_INFO(RVD, "d", "Double-precision float point"),
H A Dcpu.h64 #define RVD RV('D') macro
H A Dcsr.c1442 val & RVF && val & RVD)) { in write_misa()
/openbmc/qemu/target/riscv/kvm/
H A Dkvm-cpu.c136 KVM_MISA_CFG(RVD, KVM_RISCV_ISA_EXT_D),
574 if (riscv_has_ext(env, RVD)) { in kvm_riscv_get_regs_fp()
607 if (riscv_has_ext(env, RVD)) { in kvm_riscv_put_regs_fp()
/openbmc/qemu/linux-user/
H A Dsyscall.c8848 riscv_has_ext(env, RVD) ? in risc_hwprobe_fill_pairs()