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Searched refs:RTSR_HZE (Results 1 – 6 of 6) sorted by relevance

/openbmc/linux/drivers/rtc/
H A Drtc-sa1100.c34 #define RTSR_HZE BIT(3) /* HZ interrupt enable */ macro
60 if (rtsr & (RTSR_ALE | RTSR_HZE)) { in sa1100_rtc_interrupt()
79 writel_relaxed(rtsr & (RTSR_ALE | RTSR_HZE), info->rtsr); in sa1100_rtc_interrupt()
144 (RTSR_HZE | RTSR_ALE | RTSR_AL), info->rtsr); in sa1100_rtc_set_alarm()
H A Drtc-pxa.c38 #define RTSR_HZE (1 << 3) /* HZ interrupt enable */ macro
142 rtsr_clear_bits(pxa_rtc, RTSR_RDALE1 | RTSR_PIALE | RTSR_HZE); in pxa_rtc_irq()
198 rtsr_clear_bits(pxa_rtc, RTSR_PIALE | RTSR_RDALE1 | RTSR_HZE); in pxa_rtc_release()
285 (rtc_readl(pxa_rtc, RTSR) & RTSR_HZE) ? "yes" : "no"); in pxa_rtc_proc()
353 rtsr_clear_bits(pxa_rtc, RTSR_PIALE | RTSR_RDALE1 | RTSR_HZE); in pxa_rtc_probe()
/openbmc/linux/arch/arm/mach-pxa/
H A Dregs-rtc.h19 #define RTSR_HZE (1 << 3) /* HZ interrupt enable */ macro
/openbmc/qemu/hw/arm/
H A Dstrongarm.c248 #define RTSR_HZE (1 << 3) /* RTC 1Hz enable */ macro
288 if ((s->rtsr & RTSR_HZE) && !(s->rtsr & RTSR_HZ)) { in strongarm_rtc_timer_update()
356 s->rtsr = (value & (RTSR_ALE | RTSR_HZE)) | in strongarm_rtc_write()
/openbmc/u-boot/arch/arm/include/asm/arch-pxa/
H A Dpxa-regs.h910 #define RTSR_HZE (1 << 3) /* HZ interrupt enable */ macro
/openbmc/u-boot/include/
H A DSA-1100.h1202 #define RTSR_HZE 0x00000008 /* 1 Hz clock interrupt Enable */ macro