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Searched refs:RST_NR_PER_BANK (Results 1 – 7 of 7) sorted by relevance

/openbmc/linux/drivers/clk/mediatek/
H A Dclk-mt6795-infracfg.c65 [MT6795_INFRA_RST0_SCPSYS_RST] = 0 * RST_NR_PER_BANK + 5,
66 [MT6795_INFRA_RST0_PMIC_WRAP_RST] = 0 * RST_NR_PER_BANK + 7,
67 [MT6795_INFRA_RST1_MIPI_DSI_RST] = 1 * RST_NR_PER_BANK + 4,
68 [MT6795_INFRA_RST1_MIPI_CSI_RST] = 1 * RST_NR_PER_BANK + 7,
69 [MT6795_INFRA_RST1_MM_IOMMU_RST] = 1 * RST_NR_PER_BANK + 15,
H A Dreset.c27 data->desc->rst_bank_ofs[id / RST_NR_PER_BANK], in mtk_reset_update()
28 BIT(id % RST_NR_PER_BANK), val); in mtk_reset_update()
61 data->desc->rst_bank_ofs[id / RST_NR_PER_BANK] + in mtk_reset_update_set_clr()
63 BIT(id % RST_NR_PER_BANK)); in mtk_reset_update_set_clr()
159 data->rcdev.nr_resets = desc->rst_bank_nr * RST_NR_PER_BANK; in mtk_register_reset_controller()
220 data->rcdev.nr_resets = desc->rst_bank_nr * RST_NR_PER_BANK; in mtk_register_reset_controller_with_dev()
H A Dclk-mt8195-infra_ao.c202 [MT8195_INFRA_RST0_THERM_CTRL_SWRST] = 0 * RST_NR_PER_BANK + 0,
203 [MT8195_INFRA_RST2_USBSIF_P1_SWRST] = 2 * RST_NR_PER_BANK + 18,
204 [MT8195_INFRA_RST2_PCIE_P0_SWRST] = 2 * RST_NR_PER_BANK + 26,
205 [MT8195_INFRA_RST2_PCIE_P1_SWRST] = 2 * RST_NR_PER_BANK + 27,
206 [MT8195_INFRA_RST3_THERM_CTRL_PTP_SWRST] = 3 * RST_NR_PER_BANK + 5,
207 [MT8195_INFRA_RST4_THERM_CTRL_MCU_SWRST] = 4 * RST_NR_PER_BANK + 10,
H A Dclk-mt8188-infra_ao.c189 [MT8188_INFRA_RST1_THERMAL_MCU_RST] = 1 * RST_NR_PER_BANK + 2,
190 [MT8188_INFRA_RST1_THERMAL_CTRL_RST] = 1 * RST_NR_PER_BANK + 4,
191 [MT8188_INFRA_RST3_PTP_CTRL_RST] = 3 * RST_NR_PER_BANK + 5,
H A Dreset.h12 #define RST_NR_PER_BANK 32 macro
H A Dclk-mt8192.c951 [MT8192_INFRA_RST0_THERM_CTRL_SWRST] = 0 * RST_NR_PER_BANK + 0,
952 [MT8192_INFRA_RST2_PEXTP_PHY_SWRST] = 2 * RST_NR_PER_BANK + 15,
953 [MT8192_INFRA_RST3_THERM_CTRL_PTP_SWRST] = 3 * RST_NR_PER_BANK + 5,
954 [MT8192_INFRA_RST4_PCIE_TOP_SWRST] = 4 * RST_NR_PER_BANK + 1,
955 [MT8192_INFRA_RST4_THERM_CTRL_MCU_SWRST] = 4 * RST_NR_PER_BANK + 12,
H A Dclk-mt8186-infra_ao.c204 [MT8186_INFRA_THERMAL_CTRL_RST] = 0 * RST_NR_PER_BANK + 0,
205 [MT8186_INFRA_PTP_CTRL_RST] = 1 * RST_NR_PER_BANK + 0,