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Searched refs:RREG32_SOC15_NO_KIQ (Results 1 – 4 of 4) sorted by relevance

/openbmc/linux/drivers/gpu/drm/amd/amdgpu/
H A Dsoc15_common.h74 #define RREG32_SOC15_NO_KIQ(ip, inst, reg) \ macro
H A Dgfx_v10_0.c7315 clock_hi = RREG32_SOC15_NO_KIQ(SMUIO, 0, mmGOLDEN_TSC_COUNT_UPPER_Vangogh); in gfx_v10_0_get_gpu_clock_counter()
7316 clock_lo = RREG32_SOC15_NO_KIQ(SMUIO, 0, mmGOLDEN_TSC_COUNT_LOWER_Vangogh); in gfx_v10_0_get_gpu_clock_counter()
7317 hi_check = RREG32_SOC15_NO_KIQ(SMUIO, 0, mmGOLDEN_TSC_COUNT_UPPER_Vangogh); in gfx_v10_0_get_gpu_clock_counter()
7322 clock_lo = RREG32_SOC15_NO_KIQ(SMUIO, 0, mmGOLDEN_TSC_COUNT_LOWER_Vangogh); in gfx_v10_0_get_gpu_clock_counter()
7330 clock_hi = RREG32_SOC15_NO_KIQ(SMUIO, 0, mmGOLDEN_TSC_COUNT_UPPER_GC_10_3_6); in gfx_v10_0_get_gpu_clock_counter()
7331 clock_lo = RREG32_SOC15_NO_KIQ(SMUIO, 0, mmGOLDEN_TSC_COUNT_LOWER_GC_10_3_6); in gfx_v10_0_get_gpu_clock_counter()
7345 clock_hi = RREG32_SOC15_NO_KIQ(SMUIO, 0, mmGOLDEN_TSC_COUNT_UPPER); in gfx_v10_0_get_gpu_clock_counter()
7346 clock_lo = RREG32_SOC15_NO_KIQ(SMUIO, 0, mmGOLDEN_TSC_COUNT_LOWER); in gfx_v10_0_get_gpu_clock_counter()
7347 hi_check = RREG32_SOC15_NO_KIQ(SMUIO, 0, mmGOLDEN_TSC_COUNT_UPPER); in gfx_v10_0_get_gpu_clock_counter()
7352 clock_lo = RREG32_SOC15_NO_KIQ(SMUIO, 0, mmGOLDEN_TSC_COUNT_LOWER); in gfx_v10_0_get_gpu_clock_counter()
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H A Dgfx_v9_0.c4004 clock_hi = RREG32_SOC15_NO_KIQ(SMUIO, 0, mmGOLDEN_TSC_COUNT_UPPER_Renoir); in gfx_v9_0_get_gpu_clock_counter()
4005 clock_lo = RREG32_SOC15_NO_KIQ(SMUIO, 0, mmGOLDEN_TSC_COUNT_LOWER_Renoir); in gfx_v9_0_get_gpu_clock_counter()
4006 hi_check = RREG32_SOC15_NO_KIQ(SMUIO, 0, mmGOLDEN_TSC_COUNT_UPPER_Renoir); in gfx_v9_0_get_gpu_clock_counter()
4011 clock_lo = RREG32_SOC15_NO_KIQ(SMUIO, 0, mmGOLDEN_TSC_COUNT_LOWER_Renoir); in gfx_v9_0_get_gpu_clock_counter()
H A Dgfx_v11_0.c4968 data = RREG32_SOC15_NO_KIQ(GC, 0, regRLC_SPM_MC_CNTL); in gfx_v11_0_update_spm_vmid()