Searched refs:RL (Results 1 – 15 of 15) sorted by relevance
| /openbmc/u-boot/drivers/ddr/microchip/ |
| H A D | ddr2.c | 38 writel(SCL_BURST8 | SCL_DDR_CONNECTED | SCL_RCAS_LAT(RL) | in ddr2_phy_init()
168 ((RL - WL + 3) << 28)), &ctrl->dlycfg0); in ddr2_ctrl_init()
177 (((RL + 5) >> 4) << 29) | in ddr2_ctrl_init()
186 ((RL + 3) << 28)), &ctrl->dlycfg2); in ddr2_ctrl_init()
196 writel(ODTRDLY(RL - 3) | ODTWDLY(WL - 3) | ODTRLEN(2) | ODTWLEN(3), in ddr2_ctrl_init()
228 host_load_cmd(ctrl, 5, temp, LOAD_MODE_CMD | (RL << 28) | (2 << 24), in ddr2_ctrl_init()
241 host_load_cmd(ctrl, 9, temp, LOAD_MODE_CMD | (RL << 28) | (3 << 24), in ddr2_ctrl_init()
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| H A D | ddr2_timing.h | 17 #define RL 5 macro
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| /openbmc/openbmc/poky/meta/recipes-support/attr/acl/ |
| H A D | 0001-test-misc.test-Don-t-mix-stdout-and-stderr.patch | 26 - $ getfacl -RL d
27 + $ getfacl -RL d > /dev/null
29 + $ getfacl -RL d 2> /dev/null
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| /openbmc/u-boot/arch/arm/mach-omap2/omap4/ |
| H A D | emif.c | 25 .RL = 6,
49 .RL = 3,
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| H A D | sdram_elpida.c | 192 .RL = 6,
215 .RL = 5,
238 .RL = 3,
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| /openbmc/qemu/target/i386/emulate/ |
| H A D | x86.h | 238 #define RL(cpu, reg) (x86_reg(cpu, reg)->lx) macro
239 #define AL(cpu) RL(cpu, R_EAX)
240 #define CL(cpu) RL(cpu, R_ECX)
241 #define DL(cpu) RL(cpu, R_EDX)
242 #define BL(cpu) RL(cpu, R_EBX)
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| H A D | x86_decode.c | 1677 ptr = &RL(env, reg); in get_reg_ref()
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| /openbmc/u-boot/arch/arm/mach-omap2/omap5/ |
| H A D | emif.c | 26 .RL = 8,
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| H A D | sdram.c | 614 .RL = 8,
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| /openbmc/openbmc/meta-openembedded/meta-multimedia/recipes-multimedia/dvb-apps/files/dvb-scan-table/dvb-t/ |
| H A D | uk-Keighley | 3 # <http://www.digitaluk.co.uk/coveragechecker/main/tradeexport/BD20�5RL/NA/0/>
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| /openbmc/qemu/target/riscv/insn_trans/ |
| H A D | trans_rva.c.inc | 70 * so we can ignore AQ/RL along this path.
83 * provide the memory barrier implied by AQ/RL/TSO.
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| /openbmc/u-boot/arch/arm/mach-omap2/ |
| H A D | emif-common.c | 641 u8 RL) in get_sdram_config_reg() argument
651 config_reg |= RL << EMIF_REG_CL_SHIFT; in get_sdram_config_reg()
840 static u32 get_ddr_phy_ctrl_1(u32 freq, u8 RL) in get_ddr_phy_ctrl_1() argument
844 phy |= (RL + 2) << EMIF_REG_READ_LATENCY_SHIFT; in get_ddr_phy_ctrl_1()
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| /openbmc/openbmc/poky/meta/files/common-licenses/ |
| H A D | MS-RL | 2 Microsoft Reciprocal License (Ms-RL)
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| /openbmc/u-boot/arch/arm/include/asm/arch-mx5/ |
| H A D | imx-regs.h | 180 #define RL(x) (((x) & 0x3) << 8) macro
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| /openbmc/u-boot/arch/arm/include/asm/ |
| H A D | emif.h | 1141 u8 RL; member
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