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Searched refs:REG_PC (Results 1 – 15 of 15) sorted by relevance

/openbmc/qemu/tests/functional/
H A Dtest_x86_64_reverse_debug.py
H A Dtest_aarch64_reverse_debug.py
H A Dtest_ppc64_reverse_debug.py
H A Dreverse_debugging.py
/openbmc/qemu/linux-user/include/host/riscv/
H A Dhost-signal.h19 return uc->uc_mcontext.__gregs[REG_PC]; in host_signal_pc()
24 uc->uc_mcontext.__gregs[REG_PC] = pc; in host_signal_set_pc()
/openbmc/openbmc/meta-openembedded/meta-oe/recipes-extended/redis/redis/
H A D0006-Define-correct-gregs-for-RISCV32.patch26 + return (void*) uc->uc_mcontext.__gregs[REG_PC];
47 + (unsigned long) uc->uc_mcontext.__gregs[REG_PC],
/openbmc/openbmc/meta-openembedded/meta-oe/recipes-extended/redis/redis-7.2.8/
H A D0006-Define-correct-gregs-for-RISCV32.patch26 + return (void*) uc->uc_mcontext.__gregs[REG_PC];
47 + (unsigned long) uc->uc_mcontext.__gregs[REG_PC],
/openbmc/u-boot/arch/sh/include/asm/
H A Dptrace.h27 #define REG_PC 16 macro
/openbmc/u-boot/arch/xtensa/include/asm/
H A Dptrace.h55 #define REG_PC 0x14000000 macro
/openbmc/qemu/tests/tcg/riscv64/
H A Dnoexec.c5 return (void *)ctx->__gregs[REG_PC]; in arch_mcontext_pc()
/openbmc/qemu/util/
H A Dcpuinfo-riscv.c26 uc->uc_mcontext.__gregs[REG_PC] += 4; in sigill_handler()
/openbmc/openbmc/meta-openembedded/meta-oe/recipes-devtools/abseil-cpp/abseil-cpp/
H A D0004-abseil-ppc-fixes.patch86 return reinterpret_cast<void*>(context->uc_mcontext.__gregs[REG_PC]);
/openbmc/openbmc/meta-openembedded/meta-python/recipes-devtools/python/python3-grpcio/
H A Dabseil-ppc-fixes.patch85 return reinterpret_cast<void*>(context->uc_mcontext.__gregs[REG_PC]);
/openbmc/qemu/target/hexagon/imported/mmvec/
H A Dmacros.def204 warn("aligning misaligned vector. PC=%08x EA=%08x",thread->Regs[REG_PC],(EA));
/openbmc/qemu/target/hexagon/imported/
H A Dmacros.def425 (READ_RREG(REG_PC)), /* behavior */