| /openbmc/qemu/tests/avocado/ |
| H A D | reverse_debugging.py | 83 return self.get_reg(g, self.REG_PC)
202 REG_PC = 0x10 variable in ReverseDebugging_X86_64
205 return self.get_reg_le(g, self.REG_PC) \
223 REG_PC = 32 variable in ReverseDebugging_AArch64
247 REG_PC = 0x40 variable in ReverseDebugging_ppc64
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| /openbmc/qemu/linux-user/include/host/riscv/ |
| H A D | host-signal.h | 19 return uc->uc_mcontext.__gregs[REG_PC]; in host_signal_pc()
24 uc->uc_mcontext.__gregs[REG_PC] = pc; in host_signal_set_pc()
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| /openbmc/linux/arch/arm/nwfpe/ |
| H A D | fpa11_cpdt.c | 218 if (REG_PC == getRn(opcode)) { in PerformLDF()
266 if (REG_PC == getRn(opcode)) { in PerformSTF()
312 if (REG_PC == getRn(opcode)) { in PerformLFM()
348 if (REG_PC == getRn(opcode)) { in PerformSFM()
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| H A D | fpmodule.h | 17 #define REG_PC 15 macro
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| H A D | fpmodule.inl | 33 if (REG_PC == nReg)
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| /openbmc/openbmc/meta-openembedded/meta-oe/recipes-extended/redis/redis/ |
| H A D | 0006-Define-correct-gregs-for-RISCV32.patch | 26 + return (void*) uc->uc_mcontext.__gregs[REG_PC];
47 + (unsigned long) uc->uc_mcontext.__gregs[REG_PC],
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| /openbmc/openbmc/meta-openembedded/meta-oe/recipes-extended/redis/redis-7.2.7/ |
| H A D | 0006-Define-correct-gregs-for-RISCV32.patch | 26 + return (void*) uc->uc_mcontext.__gregs[REG_PC];
47 + (unsigned long) uc->uc_mcontext.__gregs[REG_PC],
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| /openbmc/linux/arch/sh/include/uapi/asm/ |
| H A D | ptrace_32.h | 23 #define REG_PC 16 macro
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| /openbmc/linux/arch/xtensa/include/uapi/asm/ |
| H A D | ptrace.h | 21 #define REG_PC 0x0020 macro
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| /openbmc/u-boot/arch/sh/include/asm/ |
| H A D | ptrace.h | 27 #define REG_PC 16 macro
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| /openbmc/u-boot/arch/xtensa/include/asm/ |
| H A D | ptrace.h | 55 #define REG_PC 0x14000000 macro
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| /openbmc/qemu/tests/tcg/riscv64/ |
| H A D | noexec.c | 5 return (void *)ctx->__gregs[REG_PC]; in arch_mcontext_pc()
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| /openbmc/linux/arch/alpha/kernel/ |
| H A D | ptrace.c | 71 REG_R0 = 0, REG_F0 = 32, REG_FPCR = 63, REG_PC = 64 enumerator
185 pc = get_reg(child, REG_PC); in ptrace_set_bpt()
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| /openbmc/qemu/util/ |
| H A D | cpuinfo-riscv.c | 26 uc->uc_mcontext.__gregs[REG_PC] += 4; in sigill_handler()
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| /openbmc/linux/arch/xtensa/kernel/ |
| H A D | ptrace.c | 286 case REG_PC: in ptrace_peekusr()
349 case REG_PC: in ptrace_pokeusr()
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| /openbmc/openbmc/meta-openembedded/meta-oe/recipes-devtools/abseil-cpp/abseil-cpp/ |
| H A D | 0004-abseil-ppc-fixes.patch | 86 return reinterpret_cast<void*>(context->uc_mcontext.__gregs[REG_PC]);
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| /openbmc/openbmc/meta-openembedded/meta-python/recipes-devtools/python/python3-grpcio/ |
| H A D | abseil-ppc-fixes.patch | 85 return reinterpret_cast<void*>(context->uc_mcontext.__gregs[REG_PC]);
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| /openbmc/linux/arch/arm/kernel/ |
| H A D | ptrace.c | 33 #define REG_PC 15 macro
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| /openbmc/qemu/target/hexagon/imported/mmvec/ |
| H A D | macros.def | 204 warn("aligning misaligned vector. PC=%08x EA=%08x",thread->Regs[REG_PC],(EA));
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| /openbmc/qemu/target/hexagon/imported/ |
| H A D | macros.def | 425 (READ_RREG(REG_PC)), /* behavior */
|